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general description the max11410 is a low-power, multi-channel, 24-bit delta-sigma adc with features and specifications that are optimized for precision sensor measurement. the input section includes a low-noise programmable gain amplifier (pga) with very high input impedance and available gains from 1x to 128x to optimize the overall dynamic range. input buffers provide isolation of the signal inputs from the switched-capacitor sampling network when the pga is not in use, making the adc easy to drive even with high-impedance sources. several integrated features simplify precision sensor applications. the programmable matched current sources provide excitation for resistive sensors. an additional current sink and current source aid in detecting broken sensor wires. the 10-channel input multiplexer provides the flexibility needed for complex, multi-sensor measurements. gpios reduce isolation components and ease control of switches or other circuitry. when used in single-cycle mode, the digital filter settles within a single conversion cycle. the available fir digital filter allows single-cycle settling in 16ms while providing more than 90db simultaneous rejection of 50hz and 60hz line noise. the integrated on-chip oscillator requires no external components. if needed, an external clock source may be used instead. control registers and conversion data are accessed through the spi-compatible serial interface. applications sensor measurement portable instruments resistive bridge measurement benefts and features high resolution and low noise for signal sources with wide dynamic range ? 24-bit resolution ? programmable gain amplifer with 1, 2, 4, 8, 16, 32, 64, and 128 gain options ? 90db simultaneous 60hz and 50hz power line rejection ? 3ppm typical inl with no missing codes optimized features for more efficient system design ? 10 analog inputs may be used for single-ended/ fully differential in any combination ? two dedicated/one shared differential voltage reference inputs ? on-demand offset and gain self-calibration low power for efficient systems ? 2.7v to 3.6v analog supply range ? 1.7v to 3.6v i/o supply range ? <1a sleep mode standard spi-compatible control interface selectable internal/external oscillator operating temperature range from -40c to +125c small 28-pin 4mm x 4mm tqfn package: lead-free & rohs compliant ordering information appears at end of data sheet. 19-8513; rev 0; 5/16 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga
simplifed block diagram ai n0 /r ef 0p in pu t mu lt ip le xe r re fe re nc e mu lt ip le xe r 10 a - 1600 a 0.5 a, 1 a, 10 a 0. 5 a, 1 a, 10 a gn d 3 rd -o rd er de lt a- si gm a mo du la to r di gi ta l fi lt er s (fir & si nc ) di gi ta l co nt ro l lo gi c ti mi ng cl oc k ge ne ra to r 1.8v re gu la to r ai n1 /r ef 0n ai n2 ai n3 ai n4 ai n5 ai n6 ai n7 ai n8 ai n9 re f1 p re f1 n re f2 p re f2 n gn d av dd ag nd gp io 0/ ex t_ cl k gp io 1 cs # sc lk di n do ut / in t# vd dr eg ca pr eg v ddi o ca pp ca pn pg a re f0 p re f0 n bi as vo lt ag e ma x 11410 maxim integrated 2 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 simplified block diagram ........................................................................ 2 absolute maximum ratings ...................................................................... 7 package thermal characteristics ................................................................. 7 electrical characteristics ........................................................................ 7 typical operating characteristics ................................................................ 16 pin configuration ............................................................................. 19 pin description ............................................................................... 19 detailed description ........................................................................... 21 analog inputs .............................................................................. 21 signal path considerations .................................................................... 21 bypass (direct signal path) mode ............................................................ 21 buffered mode ........................................................................... 21 pga mode .............................................................................. 21 digital gain ............................................................................. 22 noise performance .......................................................................... 23 analog supply current comparison for various operating modes .................................. 26 reference inputs ............................................................................ 26 low-power considerations .................................................................... 26 modulator duty cycle mode ................................................................ 26 sleep mode ............................................................................. 26 circuit settling time ......................................................................... 27 input multiplexer .......................................................................... 27 pga ................................................................................... 27 reference multiplexer ..................................................................... 27 excitation current source .................................................................. 27 v bias source .............................................................................. 27 sensor excitation current sources ............................................................. 27 burnout currents ............................................................................ 28 calibration ................................................................................. 28 self-calibration .......................................................................... 28 pga self-calibration ...................................................................... 29 system offset and gain calibration .......................................................... 29 sensitivity of calibration coefficients ......................................................... 29 example of self-calibration ................................................................. 29 table of contents maxim integrated 3 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
example of pga gain calibration .............................................................. 30 example of system offset calibration ........................................................... 30 gpios .................................................................................... 31 low-side power switch .................................................................... 31 example of system gain calibration .......................................................... 31 conversion data formats ..................................................................... 32 digital filter ................................................................................ 32 sequencer ................................................................................. 34 sequencer notes ......................................................................... 34 sequencer example ....................................................................... 34 spi interface ............................................................................... 37 dout/intb ............................................................................. 37 spi transactions ......................................................................... 37 register address byte ..................................................................... 38 register map ................................................................................ 39 8-bit control registerspd (0x00) ............................................................... 39 conv_start (0x01) ..................................................................... 40 seq_start (0x02) ....................................................................... 41 cal _start (0x03) ....................................................................... 41 gp0_ctrl (0x04) ........................................................................ 42 gp1_ctrl (0x05) ........................................................................ 43 gp_conv (0x06) ......................................................................... 44 gp_seq_addr (0x07) .................................................................... 44 filter (0x0 8) ........................................................................... 45 ctrl (0x09) ............................................................................. 45 source (0x0a) ......................................................................... 47 mux_ctrl0 (0x0b) ...................................................................... 48 mux_ctrl1 (0x0c) ...................................................................... 49 mux_ctrl2 (0x0d) ...................................................................... 50 pga (0x0e) ............................................................................. 51 wait_ext (0x0f) ........................................................................ 52 wait_start (0x10) ...................................................................... 52 24-bit control, data, and status registers ....................................................... 53 part_id (0x11) .......................................................................... 57 sysc_sel (0x12) ........................................................................ 58 sys_off_a (0x13) ....................................................................... 60 sys_off_b (0x14) ....................................................................... 61 table of contents (continued) maxim integrated 4 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sys_gain_a (0x15) ...................................................................... 62 sys_gain_b (0x16) ...................................................................... 63 self_off (0x17) ........................................................................ 64 self_gain_1 (0x18) ...................................................................... 65 self_gain_2 (0x19) ..................................................................... 66 self_gain_4 (0x1a) ..................................................................... 66 self_gain_8 (0x1b) ..................................................................... 67 self_gain_16 (0x1c) .................................................................... 67 self_gain_32 (0x1d) .................................................................... 68 self_gain_64 (0x1e) .................................................................... 68 self_gain_128 (0x1f) .................................................................... 69 lth resh 0 (0x 20) ........................................................................ 69 lth resh1 (0x 21) ........................................................................ 70 lth resh2 (0x 2 2) ........................................................................ 70 lthresh3 (0x23) ........................................................................ 71 lthresh4 (0x24) ........................................................................ 71 lth resh5 (0x 25) ........................................................................ 72 lth resh 6 (0x 26) ........................................................................ 72 lth resh7 (0x 27) ........................................................................ 73 uthresh0 (0x28) ........................................................................ 73 uthresh1 (0x29) ........................................................................ 74 uthresh2 (0x2a) ....................................................................... 74 uthresh3 (0x2b) ....................................................................... 75 uthresh4 (0x2c) ....................................................................... 75 uthresh5 (0x2d) ....................................................................... 76 uthresh6 (0x2e) ....................................................................... 76 uthresh7 (0x2f) ....................................................................... 77 data0 (0x30) ............................................................................ 77 data1 (0x31) ............................................................................ 78 data2 (0x32) ............................................................................ 78 data3 (0x33) ............................................................................ 79 data4 (0x34) ............................................................................ 79 data5 (0x35) ............................................................................ 80 data6 (0x36) ............................................................................ 80 data7 (0x37) ............................................................................ 81 status (0x38) ............................................................................ 81 status_ie (0x39) ......................................................................... 85 table of contents (continued) maxim integrated 5 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
16-bit sequencer registers ................................................................... 86 c (0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e) ............................................................................. 90 caddr (0x6f) .......................................................................... 90 typical application circuits ..................................................................... 91 two-rtd temperature measurement circuit (2, 3, and 4-wire) ........................................................................... 93 thermocouple measurement circuit ............................................................. 93 ordering information .......................................................................... 94 chip information .............................................................................. 94 package information .......................................................................... 94 revision history .............................................................................. 95 table 1. input-referred noise(vrms) with v ref = 2.5v, av dd = 3.3v, and inputs shorted. .................. 23 table 2. effective resolution with v ref = 2.5v, av dd = 3.3v, and inputs shorted. .......................... 24 table 3. noise-free resolution with v ref = 2.5v, av dd = 3.3v, and inputs shorted. ....................... 25 table 4. analog supply current comparison for various operating modes (typical values shown) ......................................................................... 26 table 5. gain calibration codes ................................................................. 28 table 6. offset calibration codes ................................................................ 28 table 7a. example of self-calibration ............................................................. 29 table 7b. example of pga gain calibration ........................................................ 30 table 7c. example of system offset calibration ..................................................... 30 table 7d. example of system gain calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. conversion data formats ............................................................... 32 table 9a. linef = 00 data rate and filter rejection settings .......................................... 33 table 9b. linef = 01 data rate and filter rejection settings .......................................... 33 table 9c. linef = 10 data rate and filter rejection settings .......................................... 33 table 9d. linef = 11 data rate and filter rejection settings .......................................... 33 table 10. populated sequence register example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 1. digital programmable gain example. ...................................................... 23 figure 2. spi timing diagram ................................................................... 38 list of figures list of tables table of contents (continued) maxim integrated 6 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
av dd to gnd (gnd = agnd = dgnd) .............. -0.3v to +3.6v v ddio to gnd (gnd = agnd = dgnd) ............... -0.3v to 3.6v av dd to v ddio ....................................................... -0.3v to 1.8v analog inputs (ain__, ref__) to agnd (gnd = agnd = dgnd) ...................... -0.3v to av dd + 0.3v capp, capn, v ddreg , capreg to gnd (gnd = agnd = dgnd) ....................... -0.3v to av dd + 0.3v digital inputs and outputs to gnd (gnd = agnd = dgnd) ..................... -0.3v to v ddio + 0.3v gpio inputs to gnd (gnd = agnd = dgnd) ............................................................... -0.3v to av dd + 0.3v maximum current into any pin .......................................... 50ma esd ratingll pins .............................................................. 2kv continuous power dissipation (single-layer board, t a = +70c, derate 20.8) ........ 1667mw continuous power dissipation (multilayer board, t a = +70c, derate 28.6mw/c above +70c) ............................. 2286mw operating temperature range ......................... -40c to +125c junction temperature ...................................................... +150c storage temperature range ............................ -40c to +150c lead temperature (soldering, 10 sec) ............................ +300c soldering temperature (reflow).......................................+260c (note 1) thermal resistance, single-layer board (tqfn) junction-to-ambient thermal resistance ( ja ) .......... 48c/w junction-to-case thermal resistance ( jc ) ................. 3c/w thermal resistance, four-layer board (tqfn) junction-to-ambient thermal resistance ( ja ) .......... 35c/w junction-to-case thermal resistance ( jc ) ................. 3c/w (av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units analog inputs full-scale input voltage v ref / gain absolute input voltage buffers disabled a gnd - 30mv av dd + 30mv v input voltage range unipolar 0 v ref v bipolar -v ref v ref common mode voltage range v cm ain buffers/pga disabled a gnd av dd v buffers enabled a gnd + 0.1 av dd - 0.1 pga gain = 1 to 16 a gnd + 0.1 + (v in ) (gain)/2 av dd - 0.1 - (v in ) (gain)/2 pga gain = 32 to 128 a gnd + 0.2 + (v in ) (gain)/2 av dd - 0.2 - (v in ) (gain)/2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. electrical characteristics package thermal characteristics maxim integrated 7 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units differential input current buffer disabled 1 a/v buffer enabled -13 +13 na pga enabled, note 2 -1 +1 absolute input current buffer disabled 1 a/v buffer enabled -65 +65 na pga enabled, -40c to +85c, note 2 -1 +1 pga enabled, -40c to +125c, note 2 -5 +5 input capacitance bypass mode 10 pf input sampling rate f s 246 khz system performance resolution 24 bits data rate 50/60hz fir flter, single-cycle conversions 1, 2, 4, 8, 16 50hz fir flter, single-cycle conversions 1.3, 2.5, 5, 10, 20, 35.6 sps 60hz fir flter, single-cycle conversions 1.3, 2.5. 5, 10, 20, 36.5 sinc4 flter, single-cycle conversions 1, 2.5, 5, 10, 15, 30, 60, 120, 240, 480 sinc4 flter, continuous conversions 4, 10, 20, 40, 60, 120, 240, 480, 960, 1920 sinc4 flter, duty cycle conversions 0.25, 0.63, 1.25, 2.5, 5, 10, 15, 30, 60, 120 electrical characteristics (continued) maxim integrated 8 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units data rate tolerance determined by internal clock accuracy -6 6 % integral nonlinearity inl differential input, reference buffer enabled, pga = 1, tested @ 16sps, note 4 -12 +3 +12 ppm fsr differential input, pga = 2 - 16, note 4 6 ppmfs differential input, pga = 32 - 64, note 4 11 differential input, pga = 128, note 4 15 offset error referred to modulator input. after self and system calibration; v refp - v refn = 2.5v. tested at 16sps. note 5. -25 0.5 +25 v offset error drift 50 nv/c pga gain settings 1, 2, 4, 8, 16, 32, 64,128 digital gain settings 2, 4 pga gain error no calibration, note 3 0.1 % gain = 1, after calibration, note 3 -0.002 +0.002 pga gain drift 20 ppm s/c input noise v n fir50/60hz, 16.8sps, pga = 128. see tables 1 and 4 for other conditions. 188 nv rms noise-free resolution nfr fir50/60hz, 16.8sps, pga = 1. see table 3 for other conditions. 17.2 bits normal mode rejection (internal clock) nmr 50hz/60hz fir flter, 50hz 1%, 16sps conversion, note 2 81.8 db 50hz/60hz fir flter, 60hz 1%, 16sps single-cycle conversion, note 2 94.4 50hz fir flter, 50hz 1%, 35.6sps single-cycle conversion, note 2 39.2 60hz fir flter, 60hz 1%, 35.6sps single-cycle conversion, note 2 42.3 sinc4 flter, 50hz 1%, 10sps single-cycle conversion, note 2 55.1 sinc4 flter 60hz 1%, 10sps single-cycle conversion, note 2 90.4 electrical characteristics (continued) maxim integrated 9 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units normal mode rejection (external clock) nmr 50 hz/60hz fir flter, 50hz or 60hz 1%, 16sps single-cycle conversion 96 db 50hz fir flter, 50hz 1%, 35.6sps single- cycle conversion 45 60hz fir flter, 60hz 1%, 35.6sps single- cycle conversion 49 sinc4 flter, 50hz 1%, 10sps single-cycle conversion 80 sinc4 flter, 60hz 1%, 10 sps single- cycle conversion 95 common-mode rejection cmr dc rejection, any pga gain 90 db cmr60 50/60hz rejection, pga enabled 100 power supply rejection psrra 70 80 db reference inputs reference voltage range reference buffer(s) disabled a gnd - 30m av dd + 30m v reference buffer(s) enabled a gnd + 0.1 av dd - 0.1 reference voltage input v ref = v refp - v refn 0.75 2.5 av dd v reference input current reference buffer disabled 2.1 a/v reference buffer enabled -200 61 +200 na reference input capacitance reference buffers disabled 15 pf burnout current sources current 0.5,1,10 a initial tolerance 10 % drift 0.1 %/c electrical characteristics (continued) maxim integrated 10 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units matched current sources matched current source outputs 10, 50, 75, 100, 125, 150, 175, 200, 225, 250, 300, 400, 600, 800, 1200, 1600 a current source output voltage compliance idac 250a 0 av dd - 0.7 v idac = 1.6ma 0 av dd - 1.2 initial tolerance t a = 25c, note 2 -5 1 +5 % temperature drift each idac 50 ppm/c current matching between idacs 0.1 % temperature drift matching between idacs 10 ppm/c current source output noise i n output current = 250a. sinc4 flter, 60sps continuous. noise is referred to input. 0.47 pa rms v bias outputs v bias voltage av dd /2 v v bias voltage output impedance 125k (active), 20k (pas - sive), 125k (pas - sive) electrical characteristics (continued) maxim integrated 11 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units ldo ldo output capacitance 100 nf ldo output voltage 1.62 1.8 1.98 v system timing power-on wake-up time from av dd > v por 240 s sleep wake-up time 1.25 ms pga power-up time c filter = 0 0.25 ms c filter = 20nf 2 c filter = 100nf 10 pga settling time after changing gain settings to gain = 1. c filter = 0. 0.25 ms after changing gain settings to gain = 1. c filter = 100nf. 10 after changing gain settings to gain = 128. c filter = 0. 2 input multiplexer power-up time settled to 21 bits with 10pf load 2 s input multiplexer channel-to-channel settling time settled to 21 bits with 2k external source resistor 2 s v bias power-up time active generator; settled within 1% of fnal value; c load = 1f 10 ms 125k passive generator; settled within 1% of fnal value; c load = 1f 575 20k passive generator; settled within 1% of fnal value; c load = 1f 90 v bias settling time active generator; settled within 1% of fnal value; c load = 1f 10 ms 125k passive generator; settled within 1% of fnal value; c load = 1f 605 20k passive generator; settled within 1% of fnal value; c load = 1f 100 matched current source startup time 110 s matched current source settling time 12.5 s electrical characteristics (continued) maxim integrated 12 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units power specifications analog supply av dd 2.7 3.6 v interface supply v ddio 1.7 3.6 v av dd currents sleep mode 0.5 3 a standby mode 115 150 bypass mode, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 60sps. 390 550 buffered mode, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 60sps. 425 600 pga enabled, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 60sps. t a = -40c to 105c 700 pga enabled, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 60sps. t a = -40c to 125c. 520 750 v ddio operating current all modes of operation 0.3 2 a v ddreg current 48 a avdd duty cycle power mode bypass mode, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 15sps. 280 380 a buffered mode, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 15sps. 300 400 pga enabled, idac, v bias sources off, av dd = v ref = v in = 3.6v, sinc4 flter, continuous conversions at 15sps. 400 580 spi timing specifications sclk frequency f sclk 0 8 mhz sclk period t sclk 125 ns sclk pulse-width high t ch 50 ns sclk pulse-width low t cl 50 ns electrical characteristics (continued) maxim integrated 13 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units csb fall to sclk fall setup time t css0 csb falling edge to the 1st sclk falling edge 40 ns csb rise to sclk fall hold time t csh1 applies to the last active sclk falling edge 3 ns csb rise to sclk fall t csa applies to last active sclk falling edge, aborted sequence 12 ns csb pulse-width high t cspw 40 ns sclk fall to cs fall t csf applies to the last active sclk falling edge 100 ns din to sclk rise setup time t ds 40 ns din to sclk rise hold time t dh 2 ns dout propagation delay t dot delay from the falling clock edge to the transition on dout 40 ns dout enable time t doe 0 40 ns dout disable time t doz 25 ns bus capacitance c b 20 pf logic inputs and outputs (non-gpio) input current leakage current 1 ua input low voltage v il 0.3 x v ddio v input high voltage v ih 0.7 x v ddio v input hysteresis v hys 200 mv input capacitance 5 pf output low level v ol i ol = 1ma, v ddio = 1.8v and 3.6v 0.1 x v ddio v output high level v oh i ol = 1ma, v ddio = 1.8v and 3.6v 0.9 x v ddio v high-z leakage current note 2 -100 +100 na high-z output capacitance 9 pf electrical characteristics (continued) maxim integrated 14 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
note 1: limits are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design and characterization. note 2: these specifications are not fully tested and are guaranteed by design and/or characterization. note 3: gain error does not include zero-scale errors. it is calculated as (full-scale error C offset error). after calibration, gain error is on the order of the noise. note 4: ppmfs is parts per million of full scale. note 5: after calibration, the offset voltage is on the order of the noise. (av dd = +3.3v, v ddio = +1.8v, v refp - v refn = av dd , t a = t min to t max , unless otherwise noted., t a =+25c for typical specifica - tions, unless otherwise noted, note 1 ) parameter symbol conditions min typ max units general purpose input and output (gpio) input current leakage current 1 a input low voltage v il 0.3 x v ddio v input high voltage v ih 0.7 x v ddio v input hysteresis v hys 200 mv output low level v ol i ol = 1ma, a vdd = 2.7v and 3.6v 0.1 x av dd v output high level v oh i ol = 1ma, av dd = 2.7v and 3.6v 0.9 x av dd v low-side power switch current gpio output voltage = 1v 25 ma low-side power switch impedance gpio output voltage = 1v 35 internal clock output frequency 2.3347 2.4576 2.5805 mhz internal clock output duty cycle 40 60 % external clock input frequency 2.4576 mhz external clock input duty cycle 30 70 % electrical characteristics (continued) maxim integrated 15 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(v avdd = 3.3v, v ref = 2.5v, internal clock, t a = 25c unless otherwise noted.) 0 50 100 150 200 250 -1.0 -0.5 0.0 0.5 1.0 number of occurrences input voltage (v) 16.8 sps noise histogram toc1 pga = 32, fir filter, input referred, shorted inputs, v cm = av dd /2 0 50 100 150 200 250 -0.9 -0.5 0.0 0.5 0.9 number of occurrences input voltage (v) 16.8 sps noise histogram toc2 pga = 128, fir filter, input referred, shorted inputs, v cm = av dd /2 0 200 400 600 800 1000 1200 1400 1600 1800 -1.0 -0.6 0.0 0.6 1.1 number of occurrences input voltage (v) 59.8sps noise histogram toc3 pga = 32, sinc filter, input referred shorted inputs, v cm = av dd /2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -1.0 -0.5 0.0 0.5 1.0 number of occurrences input voltage (v) 59.8sps noise histogram toc4 pga = 128, sinc filter, input - referred shorted inputs, v cm = av dd /2 -15 -10 -5 0 5 10 15 20 -50 0 50 100 150 offset votlage ( v ) temperature ( c) offset voltage vs. temperature toc5 pga = 1 pga = 32 pga = 128 fir filter, 16sps, single cycle, calibrated at room temperature -10 -8 -6 -4 -2 0 2 4 6 8 10 -50 0 50 100 150 offset votlage ( v ) temperature ( c) offset voltage vs. temperature toc06 pga = 1 pga = 32 pga = 128 fir filter, 16sps, single cycle, calibrated at each temperature -0.06 -0.04 -0.02 0 0.02 0.04 0.06 -50 0 50 100 150 gain error (%) temperature ( c) gain error vs. temperature toc07 pga = 1 pga = 32 pga = 128 fir filter, 16sps, single cycle, calibrated at room temperature -0.01 -0.0075 -0.005 -0.0025 0 0.0025 0.005 0.0075 0.01 -50 0 50 100 150 gain error (%) temperature ( c) gain error vs. temperature toc08 pga = 1 pga = 32 pga = 128 fir filter, 16sps, single cycle, calibrated at each temperature 250 300 350 400 450 500 -50 0 50 100 150 analog supply current ( a) temperature ( c) analog active supply current vs. temperature toc09 buffer mode av dd = 2.7v normal mode pga = 1 pga = 32 pga = 128 7slfdo2shudlqdudfhulvlfv maxim integrated g 16 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(v avdd = 3.3v, v ref = 2.5v, internal clock, t a = 25c unless otherwise noted.) 250 300 350 400 450 500 550 -50 0 50 100 150 analog supply current ( a) temperature ( c) analog quiescent current vs. temperature toc10 buffer mode av dd = 3.3v normal mode pga = 1 pga = 32 pga = 128 250 300 350 400 450 500 550 600 -50 0 50 100 150 analog supply current ( a) temperature ( c) analog quiescent current vs. temperature toc11 buffer mode av dd = 3.6v normal mode pga = 1 pga = 32 pga = 128 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 50 100 150 analog sleep current ( a) temperature ( c) analog sleep current vs. temperature toc12 av dd = 2.7v av dd = 3.3v av dd = 3.6v 60 70 80 90 100 110 120 130 -50 0 50 100 150 analog standby current ( a) temperature ( c) analog standby current vs. temperature toc13 av dd = 2.7v av dd = 3.3v av dd = 3.6v -8 -4 0 4 8 12 16 20 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 inl (ppm) differential input (v) inl vs. input voltage 105c toc14 pga = 1 25c - 40c -10 -5 0 5 10 15 -0.09 -0.06 -0.03 0 0.03 0.06 0.09 inl (ppm) differential input (v) inl vs. input voltage 105c toc15 pga = 32 25c - 40c 125c -30 -20 -10 0 10 20 30 -0.02 -0.012 -0.004 0.004 0.012 0.02 inl (ppm) differential input (v) inl vs. input voltage toc16 pga = 128 25c 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 -50 0 50 100 150 oscillator frequency (mhz) temperature ( c) internal oscillator frequency vs. temperature toc17 av dd = 3.0v av dd = 3.6v av dd = 2.7v av dd = 3.3v 92 94 96 98 100 102 104 106 108 110 -50 0 50 100 150 cmrr (db) temperature ( c) dc cmrr vs. temperature calibrated at each temperature toc18 pga = 1 pga = 32 pga = 128 fir filter, 16sps, single cycle typical operating characteristics (continued) maxim integrated g 17 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
(v avdd = 3.3v, v ref = 2.5v, internal clock, t a = 25c unless otherwise noted.) 80 90 100 110 120 130 140 150 0 50 100 150 dc psrr (db) gain (v/v) dc psrr vs. gain toc19 fir, 16sps fir, 40sps sinc, 60sps sinc, 240sps sinc, 120sps 250.6 250.8 251 251.2 251.4 251.6 251.8 -50 0 50 100 150 current source ( a) temperature ( c) matched current source drift toc20 i dac0 = i dac1 = 250 a i dac0 i dac1 0 5 10 15 20 25 30 35 -2.75 -2.25 -1.75 -1.25 -0.75 -0.25 0.25 0.75 number of occurences initial accuracy (%) matched current source accuracy histogram i dac0 = i dac1 = 250 a t a = 25 c toc21 0 5 10 15 20 25 30 35 40 45 50 -0.1 -0.06 -0.02 0.02 0.06 0.1 number of occurences mismatch error (%) matched current source mismatch histogram i dac = 250 a t a = 25 c toc22 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 -50 0 50 100 150 current source mismatch current ( a) temperature ( c) matched current source mismatch drift toc23 i dac0 = i dac1 = 250 a 0 5 10 15 20 25 30 35 40 45 50 55 60 0 0.5 1 1.5 2 2.5 3 i in2 , i in3 (na) (v in2 - v in3 ) (v) absolute input current vs. input voltage ( t a = - 40 c ) toc24 buffered mode, v ref1p - v ref1n = 2.5v i in2 i in3 0 5 10 15 20 25 30 35 40 45 50 55 60 0 0.5 1 1.5 2 2.5 3 i in2 , i in3 (na) (v in2 , v in3 ) (v) absolute input current vs. input voltage ( t a = +25 c ) toc25 buffered mode, v ref1p - v ref1n = 2.5v i in2 i in3 0 5 10 15 20 25 30 35 40 45 50 55 60 0 0.5 1 1.5 2 2.5 i in2 , i in3 (na) (v in2 , v in3 ) (v) absolute input current vs. input voltage ( t a = +105 c ) toc26 buffered mode, v ref1p - v ref1n = 2.5v i in2 i in3 0 5 10 15 20 25 30 35 40 45 50 55 60 0 0.5 1 1.5 2 2.5 3 i in2 , i in3 (na) (v in2 - v in3 ) (v) absolute input current vs. input voltage ( t a = +125 c ) toc27 buffered mode, v ref1p - v ref1n = 2.5v i in2 i in3 typical operating characteristics (continued) maxim integrated g 18 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
pin name function ref supply type max11410 1 ain0/ref0p channel 0 analog input/positive differential reference 0 input. when used as an analog input, may serve as either the positive or negative differential input. may also serve as current source output. when used as a reference input, ref0p must be more positive than ref0n. av dd analog input 2 ain1/ref0n channel 1 input/negative differential reference 0 input. when used as an analog input, may serve as either the positive or negative differential input. may also serve as current source output. when used as a reference input, ref0p must be more positive than ref0n. av dd analog input 3 ain2 channel 2 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 4 ain3 channel 3 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 5 capp pga output. connect 1nf capacitor across capp and capn. av dd output 6 capn pga output. connect 1nf capacitor across capp and capn av dd output 7 ain4 channel 4 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 8 ain5 channel 5 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 9 ain6 channel 6 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input pin confguration pin description maxim integrated 19 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
pin name function ref supply type max11410 10 ain7 channel 7 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 11 ain8 channel 8 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 12 ain9 channel 9 input. may serve as either the positive or negative differential input. may also serve as current source output. av dd analog input 13 agnd analog ground voltage for av dd supply. connect agnd and gnd together. n/a ground 14 avdd analog supply voltage, +2.7v to +3.6v with respect to agnd. av dd power 15 dout/intb this pin serves a dual function. serial data output: the device will drive this pin in response to a serial clock at sclk, when data is read from the internal registers. in addition to the serial data output function, the dout/intb pin also indicates an enabled interrupt condition has occurred when the pin is asserted low. to view the interrupt state on dout/intb, enable csb. v ddio digital output 16 gpio1 register-controlled, general-purpose input/output. av dd digital i/o 17 din serial data input. data present at din is shifted in to the parts internal registers in response to a serial clock at sclk, either when the part is accessed for an internal register write or for a command operation. v ddio digital input 18 csb chip select bar. active-low logic input. use csb to select the ic for access through the serial interface. csb is used for frame synchronization for communications when sclk is continuous. csb transitioning from low to high is used to reset the spi interface. v ddio digital input 19 sclk serial clock. logic input. apply an external serial clock to this input to issue commands to or access data. v ddio digital input 20 vddreg digital regulator supply, connect to avdd. av dd power 21 gpio0 register controlled general purpose input/output and external clock signal input. when external clock mode is selected (extclk = 1), provide a 2.4576mhz clock signal at clk. other frequencies can be used, but the data rate and digital flter notch frequencies scale accordingly. av dd digital i/o 22 capreg digital regulator output. connect a 100nf capacitor from capreg to agnd. av dd power 23 vddio digital interface supply (+1.8v to +3.6v). v ddio power 24 gnd ground reference for v ddio . connect to agnd. n/a ground 25 ref2p positive differential reference 2 input. ref2p must be more positive than ref2n. av dd analog input 26 ref2n negative differential reference 2 input. ref2p must be more positive than ref2n. av dd analog input 27 ref1p positive differential reference 1 input. ref1p must be more positive than ref1n. av dd analog input 28 ref1n negative differential reference 1 input. ref1p must be more positive than ref1n. av dd analog input pin description (continued) maxim integrated 20 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
detailed description this low-power, multi-channel, 24-bit delta-sigma adc has features and specifications that are optimized for precision measurement of sensors and other analog signal sources. the input section includes a low-noise programmable gain amplifier (pga) with very high input impedance and available gains from 1x to 128x to optimize the overall dynamic range. low-power input buffers may be enabled to provide isolation of the signal source from the modulator's switched-capacitor sampling network when the pga is not in use, reducing the supply current requirements compared to the pga. several integrated features simplify precision sensor applications. the programmable matched current sources provide excitation for resistive sensors; sixteen different current levels are available, allowing sensor full-scale range to be tuned for optimum signal-to-noise ratio. an additional current sink and current source supply small current levels to aid in detecting broken sensor wires. the 5-channel differential/10-channel single-ended multiplexer provides the flexibility needed for complex multi-sensor measurements. gpios reduce isolation components and ease control of switches or other circuitry. the adc can operate in continuous conversion mode at data rates up to 1920sps, and in single-cycle conversion mode at rates up to 480sps. when used in single-cycle mode, the digital filter settles within a single conversion cycle. the available fir digital filter allows single-cycle settling in 16ms while providing more than 90db simultaneous rejection of 50hz and 60hz line noise. the integrated on-chip oscillator requires no external components. if needed, an external clock source may be used instead. control registers and conversion data are accessed through the spi-compatible serial interface. analog inputs the ten analog inputs (ain0Cain9) are configurable for differential/single-ended operation. for each conversion, the input multiplexer can be configured such that any of the ten analog inputs or avdd can be used as the positive input. additionally, any of the ten analog inputs or agnd can be used as the negative input for the differential measurement. the multiplexer outputs may either drive the adc inputs directly or drive low-power buffers. they then drive the adc or the pga inputs. ain0 and ain1 are internally connected to the reference multiplexer. when used as reference inputs, they serve as ref0p and ref0n. each of the two current sources (idac0 and idac1) can be routed to any of the ten analog inputs. the bias voltage source (v bias ) can be routed to any of analog inputs ain0Cain7. signal path considerations three signal-path options are available to trade power- supply current against input impedance, gain, and input voltage range by enabling the pga or the input buffers, or bypassing both and driving the modulator directly. the pga control register selects among these options, which are summarized below. bypass (direct signal path) mode in bypass mode, the multiplexer outputs are directly connected to the adc modulator inputs. in this mode, the input buffer and the pga are disabled for minimum power-supply current. this mode allows input voltages from v agnd - 30mv to v avdd + 30mv, and adds no amplifier noise to the signal. input bias current is typically 1a/v, which is appropriate when driving with a low source resistance. for smaller signal amplitudes, digital gains of 2 and 4 are available when using the direct signal path. see the digital gain section for more information. buffered mode in buffered mode, the multiplexer outputs drive the inputs to the low-power signal buffers, which then drive the adc modulator inputs. selecting buffered mode disables the pga. input voltages from v agnd + 100mv to v avdd - 100mv are accepted in this mode, and no amplifier noise is added to the signal. the input bias current, typically 61na, is significantly less than that in the direct mode, so higher source resistances may be accommodated without causing appreciable errors. enabling the input buffers increases the power supply current by 35a (typical) compared to the bypassed (direct signal path) mode. as with the bypassed mode, digital gains of 2 and 4 are available when using the buffered mode. see the digital gain section for more information. pga mode the programmable gain amplifier (pga) provides gains of 1, 2, 4, 8, 16, 32, 64, or 128. selecting pga mode enables the pga, connects the pga inputs to the multiplexer outputs, connects the pga outputs to the adc modulator inputs, and disables the low-power input buffers. the pga accepts input voltages from v agnd + 100mv to v avdd - 100mv for gains up to 16, and v agnd + 200mv to v avdd - 200mv for gains from 32 to 128. when enabled, the pga supply current is typically 130a. maxim integrated 21 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
input current in pga mode is much lower than in the buffered or direct modes, so the pga mode is a good choice for maintaining precision when source resistances are high. note that the input current in pga mode is dominated by multiplexer leakage current, and is highest when the input voltage, including that of unused inputs, is nearest avdd or gnd. for applications that are most sensitive to the effects of input current, connect any unused inputs to a voltage near av dd /2. note that the maximum usable gain will be limited by the reference voltage and input voltage. ensure that the differential input voltage multiplied by the pga gain is less than or equal to the reference voltage: v in x gain v ref where v in = differential input voltage gain = pga gain v ref = reference voltage also ensure that the input common-mode voltage (v cm ) falls within the acceptable common-mode voltage range of the pga: 200mv + (v in x gain)/2 v cm a vdd C 200mv - (v in x gain)/2 for gains of 32 to 128 or 100mv + (v in x gain)/2 v cm a vdd - 100mv - (v in x gain)/2 for gains of 1 to 16 where v cm = (ain_p- ain_n)/2 digital gain programmable digital gain settings of 2 and 4 are available in the direct and buffered modes. select the desired gain using the gain bits of the pga register. digital gain selections greater than or equal to 4 will result in digital gain equal to 4. the input range is 0v to v ref /gain for unipolar conversions or v ref /gain for bipolar conversions. the modulator produces 32 bits of data, and for unity gain, the 8 lsbs are truncated before the data is stored in the 24-bit conversion data registers. selecting a digital gain of 2 causes the msb and the 7 lsbs to be discarded, thus producing 24 bits of data with an effective gain of 2. note that, for any data rate, the noise floor remains constant, independent of the digital gain setting. digital gain is useful for systems whose input noise is dominated by the source, or systems that can take advantage of averaging multiple readings to improve effective resolution. for cases when the output noise is below an lsb, using digital gain can decrease the input-referred noise at the expense of reduced dynamic range. figure 1. digital programmable gain example. maxim integrated 22 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
noise performance the input-referred noise depends on the selected data rate, filter, input signal path (bypass, buffer, or pga), and the pga gain (when selected). this is illustrated in the tables below. table 1 shows input-referred noise voltage (in v rms ). table 2 shows effective resolution, which is defined as: effective resolution = log 2 (fsr/rms noise), where fsr is the full-scale input range (5v in bipolar mode with a 2.5v reference), and rms noise is the input-referred rms noise. the third table shows noise-free resolution (nfr), which is defined as nfr = log 2 (fsr/p-p noise), where fsr is the full-scale input range, (5v in bipolar mode with a 2.5v reference), and p-p noise is 6.6 times the input-referred rms noise. values shown are for continuous conversions. single- cycle data rates are similar for the fir filters, and are one- fourth the continuous data rate for the sinc4 filter. note that higher pga gain reduces the input-referred noise, but because the input voltage range is reduced, the effective resolution decreases. filter rate (sps) by - pass buf - fer pga 1x pga 2x pga 4x pga 8x pga 16x pga 32x pga 64x pga 128x fir50/60 1 0.648 0.681 0.372 0.248 0.095 0.058 0.069 0.067 0.057 0.051 fir50/60 2.1 3.241 3.128 3.489 1.747 0.807 0.430 0.187 0.109 0.078 0.057 fir50/60 4.2 4.398 4.256 4.758 2.350 1.223 0.599 0.303 0.175 0.108 0.113 fir50/60 8.4 4.511 4.428 5.259 2.529 1.326 0.684 0.373 0.218 0.152 0.139 fir50/60 16.8 4.743 4.621 5.179 2.575 1.367 0.633 0.399 0.247 0.211 0.188 fir50 1.3 1.716 1.741 1.589 0.833 0.388 0.169 0.082 0.065 0.068 0.055 fir50 2.7 3.656 3.640 4.009 2.053 0.983 0.505 0.245 0.119 0.087 0.091 fir50 5.3 4.374 4.315 4.912 2.480 1.252 0.631 0.312 0.185 0.127 0.121 fir50 10.6 4.469 4.412 5.306 2.606 1.312 0.647 0.347 0.203 0.151 0.141 fir50 21.3 4.604 4.511 5.363 2.655 1.351 0.680 0.386 0.230 0.232 0.199 fir50 39.9 4.710 4.571 5.317 2.633 1.349 0.709 0.449 0.323 0.265 0.291 fir60 1.3 1.721 1.765 1.470 0.794 0.370 0.160 0.072 0.072 0.056 0.068 fir60 2.7 3.677 3.719 3.987 1.988 1.030 0.504 0.230 0.147 0.093 0.061 fir60 5.3 4.303 4.417 4.951 2.473 1.220 0.636 0.309 0.168 0.141 0.121 fir60 10.6 4.663 4.522 5.174 2.636 1.344 0.632 0.330 0.235 0.190 0.182 fir60 21.3 4.781 4.672 5.449 2.780 1.336 0.760 0.369 0.268 0.219 0.225 fir60 39.9 4.499 4.726 5.116 2.711 1.293 0.719 0.456 0.373 0.222 0.290 sinc4 1.1 0.399 0.436 0.156 0.106 0.074 0.062 0.074 0.057 0.040 0.039 sinc4 2.5 3.565 3.573 3.899 1.954 0.982 0.479 0.222 0.111 0.070 0.062 sinc4 5 4.432 4.339 4.854 2.435 1.239 0.611 0.305 0.171 0.104 0.079 sinc4 10 4.542 4.591 5.192 2.602 1.274 0.664 0.339 0.190 0.135 0.134 sinc4 59.8 4.920 4.508 5.066 2.658 1.284 0.655 0.297 0.281 0.214 0.234 sinc4 119.7 2.736 2.459 3.045 1.553 0.959 0.620 0.367 0.355 0.293 0.276 sinc4 239.4 2.762 3.000 3.366 1.683 0.948 0.596 0.540 0.473 0.383 0.365 sinc4 478.7 3.414 2.766 2.758 1.623 1.023 0.685 0.458 0.562 0.478 0.536 sinc4 957.4 4.434 3.840 4.503 2.462 1.603 1.104 0.774 1.082 0.692 0.725 sinc4 1914.8 24.496 24.785 25.092 14.761 5.831 3.855 2.152 1.332 1.115 1.038 table 1. input-referred noise(v rms ) with v ref = 2.5v, av dd = 3.3v, and inputs shorted. maxim integrated 23 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
filter rate (sps) by - pass buf - fer pga 1x pga 2x pga 4x pga 8x pga 16x pga 32x pga 64x pga 128x fir50/60 1 22.880 22.808 23.682 23.267 23.652 23.354 22.112 21.150 20.392 19.554 fir50/60 2.1 20.557 20.608 20.451 20.449 20.563 20.470 20.672 20.455 19.934 19.395 fir50/60 4.2 20.117 20.164 20.003 20.021 19.963 19.992 19.975 19.767 19.462 18.401 fir50/60 8.4 20.080 20.107 19.859 19.915 19.847 19.800 19.677 19.448 18.971 18.097 fir50/60 16.8 20.008 20.045 19.881 19.889 19.802 19.912 19.578 19.274 18.500 17.668 fir50 1.3 21.475 21.454 21.585 21.518 21.620 21.820 21.863 21.205 20.131 19.432 fir50 2.7 20.383 20.390 20.250 20.216 20.279 20.239 20.283 20.328 19.776 18.713 fir50 5.3 20.125 20.144 19.957 19.943 19.929 19.917 19.934 19.690 19.230 18.302 fir50 10.6 20.094 20.112 19.846 19.872 19.861 19.881 19.781 19.557 18.979 18.084 fir50 21.3 20.051 20.080 19.831 19.845 19.819 19.809 19.627 19.371 18.358 17.585 fir50 39.9 20.018 20.061 19.843 19.857 19.822 19.750 19.410 18.883 18.169 17.036 fir60 1.3 21.470 21.433 21.698 21.587 21.688 21.902 22.059 21.053 20.422 19.137 fir60 2.7 20.375 20.359 20.258 20.262 20.211 20.241 20.374 20.020 19.681 19.300 fir60 5.3 20.148 20.110 19.946 19.947 19.967 19.906 19.946 19.824 19.078 18.300 fir60 10.6 20.032 20.077 19.882 19.855 19.827 19.916 19.851 19.344 18.652 17.710 fir60 21.3 19.996 20.030 19.808 19.778 19.835 19.649 19.693 19.153 18.447 17.405 fir60 39.9 20.084 20.013 19.899 19.815 19.883 19.729 19.388 18.677 18.426 17.040 sinc4 1.1 23.580 23.453 24.933 24.498 24.002 23.266 22.015 21.385 20.892 19.923 sinc4 2.5 20.420 20.416 20.290 20.287 20.280 20.315 20.427 20.425 20.088 19.258 sinc4 5 20.106 20.136 19.974 19.970 19.944 19.965 19.967 19.799 19.518 18.921 sinc4 10 20.070 20.055 19.877 19.874 19.904 19.843 19.814 19.646 19.145 18.156 sinc4 59.8 19.955 20.081 19.913 19.843 19.893 19.863 20.006 19.084 18.476 17.352 sinc4 119.7 20.801 20.955 20.647 20.619 20.314 19.944 19.701 18.747 18.026 17.111 sinc4 239.4 20.788 20.668 20.503 20.503 20.331 19.999 19.143 18.335 17.639 16.706 sinc4 478.7 20.482 20.786 20.790 20.555 20.220 19.800 19.380 18.084 17.320 16.154 sinc4 957.4 20.105 20.312 20.083 19.954 19.573 19.111 18.623 17.140 16.784 15.718 sinc4 1914.8 17.639 17.622 17.604 17.370 17.710 17.307 17.148 16.840 16.096 15.200 table 2. effective resolution with v ref = 2.5v, av dd = 3.3v, and inputs shorted. maxim integrated 24 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
filter rate (sps) by - pass buf - fer pga 1x pga 2x pga 4x pga 8x pga 16x pga 32x pga 64x pga 128x fir50/60 1 20.158 20.085 20.959 20.545 20.929 20.631 19.389 18.427 17.670 16.831 fir50/60 2.1 17.835 17.886 17.728 17.726 17.841 17.748 17.950 17.732 17.211 16.672 fir50/60 4.2 17.394 17.442 17.281 17.299 17.241 17.270 17.252 17.045 16.740 15.679 fir50/60 8.4 17.358 17.384 17.136 17.192 17.124 17.078 16.955 16.726 16.248 15.375 fir50/60 16.8 17.285 17.323 17.158 17.166 17.080 17.190 16.856 16.551 15.777 14.946 fir50 1.3 18.752 18.731 18.863 18.795 18.898 19.098 19.140 18.483 17.409 16.709 fir50 2.7 17.661 17.667 17.528 17.493 17.556 17.517 17.561 17.605 17.053 15.991 fir50 5.3 17.402 17.422 17.235 17.221 17.207 17.195 17.211 16.967 16.508 15.579 fir50 10.6 17.371 17.390 17.123 17.149 17.139 17.158 17.059 16.835 16.257 15.362 fir50 21.3 17.328 17.358 17.108 17.122 17.096 17.087 16.904 16.649 15.636 14.863 fir50 39.9 17.295 17.338 17.120 17.134 17.099 17.028 16.687 16.160 15.446 14.313 fir60 1.3 18.747 18.711 18.976 18.864 18.966 19.179 19.337 18.331 17.699 16.414 fir60 2.7 17.652 17.636 17.536 17.540 17.489 17.519 17.652 17.297 16.959 16.578 fir60 5.3 17.426 17.388 17.223 17.225 17.244 17.184 17.224 17.101 16.355 15.577 fir60 10.6 17.310 17.354 17.160 17.133 17.104 17.194 17.129 16.621 15.929 14.987 fir60 21.3 17.274 17.307 17.085 17.056 17.113 16.926 16.970 16.431 15.724 14.683 fir60 39.9 17.361 17.290 17.176 17.092 17.160 17.006 16.665 15.955 15.703 14.318 sinc4 1.1 20.857 20.730 22.211 21.775 21.279 20.543 19.293 18.662 18.169 17.201 sinc4 2.5 17.697 17.694 17.568 17.565 17.557 17.593 17.704 17.703 17.366 16.536 sinc4 5 17.383 17.414 17.252 17.247 17.222 17.242 17.244 17.076 16.796 16.199 sinc4 10 17.348 17.332 17.155 17.152 17.182 17.121 17.092 16.924 16.423 15.433 sinc4 59.8 17.232 17.358 17.190 17.121 17.170 17.141 17.284 16.362 15.753 14.629 sinc4 119.7 18.079 18.233 17.924 17.896 17.592 17.221 16.979 16.025 15.303 14.388 sinc4 239.4 18.065 17.946 17.780 17.780 17.608 17.277 16.421 15.612 14.916 13.983 sinc4 478.7 17.760 18.063 18.067 17.833 17.498 17.077 16.657 15.362 14.597 13.431 sinc4 957.4 17.383 17.590 17.360 17.231 16.851 16.389 15.900 14.417 14.061 12.995 sinc4 1914.8 14.917 14.900 14.882 14.647 14.987 14.584 14.426 14.118 13.374 12.478 table 3. noise-free resolution with v ref = 2.5v, av dd = 3.3v, and inputs shorted. maxim integrated 25 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
reference inputs there are three selectable differential reference voltage inputs. select the reference input using bits ref_ sel<2:0> in the ctrl register. either vrefp, vrefn, or both may be buffered, as determined by the refbufp_ en and refbufn_en bits. with the reference buffer disabled, the input current is a few microamps (2.1a/v, typical). enabling a reference buffer reduces the reference input current to 65na, typical. with the buffer enabled, the common-mode voltage range for v refp and v refn is between 100mv and v avdd - 100mv. with the buffer disabled, the common-mode range is between gnd and v avdd . selectable buffers allow flexibility in using resistive voltage references. for example, if a voltage reference is generated by driving a current through a grounded reference resistor, v refn may be unbuffered, allowing it to be connected directly to gnd, while v refp is buffered, helping reduce the effect of input bias current on the reference voltage. low-power considerations several operating modes help to optimize power and performance. as discussed in the signal path considerations section, applications that do not require the gain or low input bias current available in pga mode can reduce supply current by 130a by disabling the pga. for low-impedance sources, the input buffers may be disabled for further power savings. similarly, the reference buffers may be disabled when the source resistance is low. the modulator has a selectable duty cycle mode for low power at lower sampling rates. the ic may be placed into sleep mode between conversions to reduce the average power-supply current. modulator duty cycle mode in addition to its normal operating mode, the modulator can be operated in a 1/4 duty cycle mode to reduce power consumption for a given data rate at the expense of noise. the noise performance of a ? adc generally improves when increasing the osr (lowering the output data rate) because more samples of the internal modulator can be averaged to yield one conversion result. in applications where power consumption is critical, the improved noise performance at low data rates may not be required. for these applications, the internal duty cycling mode can yield significant power savings by periodically entering a low-power state between conversions. in principle, the modulator runs in normal mode with a duty cycle of 25%, performing one normal conversion and then automatically entering a low-power state for three consecutive conversion cycles. the noise performance in duty-cycle mode is therefore comparable to the noise performance in normal mode at four times the data rate. the duty-cycle mode can be selected using direct, buffered, or pga signal paths. neither the input buffers nor pga are duty cycled while in duty cycle mode. select duty-cycle mode using the conv_type bits in the conv_start register. to minimize current consumption in duty-cycle mode, set the signal path for an appropriate low-power mode (see the signal path considerations section). sleep mode sleep mode (controlled by the pd register) powers down all analog circuitry including the internal oscillator, resulting in 0.5a typical current consumption. exit sleep mode either by writing to the pd register or (when enabled) by using a gpio trigger. function supply current input range input current normal conversion, 60sps, buffers and pga off (bypass mode) 390 agnd - 30mv to av dd + 30mv 1a/v duty-cycle conversion, 15sps, buffers and pga off (bypass mode) 280 agnd - 30mv to av dd + 30mv 1a/v sleep mode 0.5a n/a input buffers 35a agnd + 100mv to av dd - 100mv 65na pga 130a agnd + 100mv to av dd - 100mv 1na reference buffers disabled agnd - 30mv to av dd + 30mv 2.1a/v reference buffers enabled (each) 17.5a agnd + 100mv to av dd - 100mv 61na table 4. analog supply current comparison for various operating modes (typical values shown) maxim integrated 26 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
circuit settling time the input to the adc will require some time to settle after changing the state of the multiplexer, pga, current sources, and other analog components. when using the sequencer, insert appropriate wait times when changing the state of any of these components. input multiplexer settling time for changes to the state of the input multiplexer depends on several factors. these include the delay time of the nonoverlap circuits and the on-resistance of the multiplexer switches, but are dominated by the output impedance of the external source, the impedance (cables, protection components, etc.) between the external source and the multiplexer, any input filter capacitance, the 10pf capacitance on the input to the pga and modulator blocks, and whether or not the i dac current sources or the v bias source are being used. to obtain an accurate conversion, wait until the multiplexer is fully settled before starting a new conversion. with no added capacitance at the inputs, the settling time after a multiplexer channel change with a 2k source is typically 2s. pga pga settling time is primarily limited by the external pga filter. a 100nf external capacitor across capp and capn reduces noise by limiting the bandwidth of the pga. this results in a 2khz single-pole lowpass filter at the pga's output. settling to 22-bit accuracy (0.25ppm) requires 15.25 time constants or 7.6ms for a 2khz bandwidth. therefore, the pga typically dominates the settling time of the input when changing multiplexer settings or changing the pga's gain. reference multiplexer settling time for the reference input multiplexer is similar to that of the input multiplexer but with less complexity, as the reference multiplexer has fewer channels and does not have the i dac current sources or the v bias source as possible inputs. the delay is still dependent on the on-resistance of the reference multiplexer switches, the impedance between the reference source and the reference multiplexer, the output impedance of the reference source, and the input capacitance of the modu - lator. for accurate conversions, it is important to wait until the reference multiplexer is fully settled before starting a new conversion. normally the reference should be located close to the reference inputs, so the resistance between the source and the input should be negligible. if the reference source is an active voltage reference, the source impedance should be low enough to ignore. in some cases, the reference source may be a resistor with a value of a few kilohms. so long as the source resistance is less than around 10k, the settling time contribution from the reference source resistance will be less than 1s and can generally be ignored. excitation current source enabling/disabling the current source(s) will require time for any input capacitance to charge or discharge. this can be especially important when external capacitors have been added at the inputs for noise filtering. v bias source the v bias source generates a bias voltage equal to v dd /2. there are three v bias modes, controlled by the v bias register field. the first mode is an active bias generator featuring a class ab output stage with a series 125k resistor to create a nominal output impedance of 125k. the active bias generator mode reduces current and channel to channel crosstalk. in active mode, if the output is not settled to v dd /2, the series resistor is bypassed by a separate low-impedance class ab output stage to decrease settling time. when the output settles to v dd /2, the resistor is reasserted for improved noise filtering. the second and third modes create the v bias with resistive voltage-dividers to offer fixed output impedance (either 125k or 20k) at the expense of increased current consumption. the 125k mode offers increased supply noise filtering at the expense of increased settling time. the 20k mode offers reduced settling time, but is higher in current consumption and offers less supply noise filtering. the bias voltage can be switched into the input channels via the v bias_sel register field. sensor excitation current sources the matched current sources can be programmed to provide 16 different levels of matched currents from 10a to 1600a with 10% accuracy, 0.1% matching, and 50ppm/c temperature drift from -40c to +85c. either current source or both may be enabled, and each current source may be connected to any one of the ten analog inputs. note that only one current source may be connected to any input, and a current source may not be connected to an input that has v bias connected to it. maxim integrated 27 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
burnout currents the internal, selectable 1a, 5a, and 10a burnout current source and sink may be used to detect a sensor fault or wire break. when enabled, the current source is connected to the selected positive analog input (ainp) and the current sink is connected to the selected negative analog input (ainn). in case of an open circuit in the sensor input path, these burn-out currents pull the positive input towards av dd and the negative input towards agnd, resulting in a full- scale reading. (note that a full-scale reading may also indicate that the sensor is overdriven or that the reference voltage is absent.) calibration the adc can, on demand, automatically calibrate its internal offset and gain errors as well as system offset and gain errors, and store the calibration values in dedicated registers. the calibration register value defaults are zero (offset) and one (gain). calibration values may be calculated and stored automatically via a cal_start command or written directly to the registers through the serial interface. the cal_start command selects the type of calibration to be performed (self-calibration, pga gain calibration, system calibration) and initiates the calibration cycle. there is a separate gain calibration register for each pga gain. calibration values are applied to the conversion results stored in the data registers according to the following equation: data[0:7] = sys_gain_[a,b] x ( ( (conversion - self_off) x self_gain[1:128] ) - sys_off_[a,b] ) where data[0:7] is the adc data result destination register, selected by the dest[3:0] register field, conversion is the adcs conversion result before calibration results are applied, self_gain[1:128] is the internal gain correction value for the selected gain. self_off is the internal offset correction value, sys_gain_[a,b] is the selected system gain correction value, and sys_off_[a,b] is the selected system offset correction value. all calibration operations are performed at the filter settings programmed into the linef[1:0] and rate[3:0] registers. there are two sets of system calibration registers, a and b. either a, b, or neither set can be applied to the adc conversion result, selectable by the sysc_sel register. note that calibration routines are performed using the conversion rate, pga gain, and filter settings in the control registers. in general, slower conversion rates will exhibit lower noise and will therefore produce more accurate calibration. self-calibration in self-calibration, the required connections to zero and full scale are made internally using the pga gain setting set in the gain register. self-calibration is typically sufficient to achieve offset and gain accuracy on the order of the noise. when gain is 1, self calibration provides 20ppm of typical full-scale accuracy. the self-calibration routine does not include external effects such as source resistance of the signal driving the input pins, which can change the offset and gain of the system. the range of digital gain correction is from 0.5x to 2.0x. the range of offset correction is v ref /4. the tables below show example values for gain and offset calibration codes. table 5. gain calibration codes table 6. offset calibration codes code description gain code maximum gain correction 1.999999881 0xffffff 1 lsb greater than unity gain 1 + 1/2 23 0x800001 unity gain 1.000000 0x800000 1 lsb less than unity gain 1 - 1/2 23 0x7fffff minimum recommended gain correction 0.5 0x400000 zero gain 0 0x000000 code description offset code maximum offset correction 0.25v ref 0x7fffff positive 0.25lsb (bipolar) or 0.5lsb (unipolar) 0.25v ref /(2 23 - 1) 0x000001 zero offset correction 0v 0x000000 negative 0.25lsb (bipolar) or 0.5lsb (unipolar) - 0.25v ref /(2 23 - 1) 0xffffff minimum offset correction - 0.25v ref (1+1/(2 23 - 1)) 0x800000 maxim integrated 28 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
pga self-calibration to ensure the lowest possible gain error, eight separate self-gain calibration registers store the calibration factors for each pga gain from 1x to 128x. when performing gain calibration, the register corresponding to the currently selected pga gain will be updated. perform a pga gain calibration for each pga gain setting that will be used. not doing so will yield errors for conversions performed using the gains that have not been calibrated. self calibration will update the 1x self gain register. system offset and gain calibration a system calibration enables calibration of system zero scale and system full scale by presenting a zero-scale signal or a full-scale signal to the selected input pins and initiating a system zero-scale or system gain calibration command. as an alternative to automatic generation of the system calibration values, values may be directly written to the internal calibration registers to achieve any digital offset or scaling required. the range of digital offset correction is v ref /4. the range of digital gain correction is from 0.5x to 2.0x. the resolution of offset correction is 0.5 lsb. automatic system calibration requires applying the appropriate external signals to the selected ain inputs. therefore, the input multiplexer must be properly configured prior to system calibration. two sets of system calibration coefficients may be created and stored (sys_off_a and sys_gain_a, and sys_off_b and sys_gain_b). conversions may be performed using either or neither of these sets of coefficients. request a system offset calibration by presenting a system zero-scale signal level to the input pins and programming the cal_start register with the appropriate value. the sys_off_a or sys_off_b register then updates with the value that corrects the chip zero scale. request a system gain calibration by presenting a system full-scale signal level to the input pins and programming the cal_start register with the appropriate value. the sys_gain_a or sys_gain_b register then updates with the value that corrects the chip full scale. a system offset calibration is required prior to system gain calibration to ensure accurate gain calculation. sensitivity of calibration coeffcients calibration needs to be repeated if external factors change. both offset and gain calibration (pga gain = 1) should be performed if av dd supply voltage changes. temperature change affects the calibration accuracy to a much lesser extent (10c change results in 0.2ppm offset error drift and 0.5ppm gain error drift). for gain settings >1, the pga has reduced sensitiv - ity to supply changes compared to the modulator (28ppm over supply range) but it is still comparable to the electrical characteristics table specification. therefore, it is a good idea to recalibrate in the unlikely case that the supply voltage changes from the minimum av dd to the maximum av dd and vice versa. note that calibration is done at the currently selected data rate, so for best results, set the data rate to a value equal to or lower than the lowest rate that will be used for conversions. table 7a. example of self-calibration step description register comments 1 select filter and rate filter (0x08) for best results, select a rate no faster than the rate that will be used for conversions. a slower rate will result in more accurate calibration. this will determine the time required to execute a calibration. 2 select clock source and format. ctrl (0x11) for best results, select the clock source (internal or external) that will be used for conversions. if external clock is selected, ensure that the external clock is operating before beginning calibration. format selection doesnt affect results. 3 start calibration cal_start write xxxxx000 to cal_start. two conversions will execute at the rate controlled by the filter register. the self_offset and self_gain_1 registers will be updated. maxim integrated 29 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
table 7b. example of pga gain calibration table 7c. example of system offset calibration step description register comments 1 apply system zero n/a apply the input voltage that should result in a conversion result of 0 to appropriate analog input(s). 2 select filter and rate ctrl (0x11) for best results, select a rate no faster than the rate that will be used for conversions. a slower rate will result in more accurate calibration. 3 select reference input ref (0x09) for best results, select a reference voltage equal to or near value that will be used for conversions. 4 set input multiplexer mux_cntrl0 (0x0b) select the inputs to which system zero is applied. 5 select gain and signal path pga (0x0e) for best results, select the signal path that will be used for conversions. gain selection doesnt affect results. 6 select clock source and format ctrl (0x11) for best results, select the clock source (internal or external) that will be used for conversions. if external clock is selected, ensure that the external clock is operating before beginning calibration. format selection doesnt affect results. 7 select system offset and start calibration cal_start write xxxxx100 to store in sys_off_a register or xxxxx110 to store in sys_ off_b register. step description register comments 1 select filter and rate filter (0x08) for best results, select a rate no faster than the rate that will be used for conversions. a slower rate will result in more accurate calibration. filter selection doesnt affect results. 3 select gain and signal path pga (0x0e) for best results, select signal path that will be used for conversions. gain selection causes calibration value to be saved in the associated self_gain_ register and applied whenever the associated gain is selected. 4 select clock source and format ctrl (0x11) for best results, select the clock source (internal or external) that will be used for conversions. if external clock is selected, ensure that the external clock is operating before beginning calibration. format selection doesnt affect results. 5 select pga gain and start calibration cal_start write xxxxx001 to cal_start. one conversion will execute at the rate controlled by the filter register. the self_gain__ register for the selected gain will be updated. maxim integrated 30 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
low-side power switch the gpio pins can be configured to function as a low- side power switch with less than 35 on-resistance (25ma switch current) to reduce system power consumption in bridge sensor applications by powering down a bridge circuit between conversions. select automatic low-side switch operation by setting the gp_osel and gp_dir register bits: gp0_ctrl = 1000_0101 (switch normally open, closed during adc conversions) "manually" control the low-side power switch by configuring a gpio as an open-drain output, and switch between state logic 0 and logic 1: gp0_ctrl = 1000_0100 (logic 0, switch closed) gp0_ctrl = 1000_0100 (logic 1, switch open) gp0_ctrl = 1000_0100 (logic 0, switch closed) gpios two general-purpose digital ios increase the adc's flexibility. when used as an output, a gpio can be used as a microcontroller interrupt, a control signal for a multiplexer or multichannel switch, or a modulator clock output. gpio pins configured as outputs operate on the avdd rail. care should be taken when using the gpio pins in input mode to avoid bringing the signal above v avdd + 0.3v. when configured as an input, a gpio can be used as an external clock input, an adc start control, or a sequence start control. when using gpio0 as external clock input (extclk = 1), apply a 2.4576mhz clock signal to the pin. other frequencies can be used, but the data rate and digital filter notch frequencies scale accordingly. gpio pins configured as inputs accept inputs at v ddio levels (not to exceed av dd ). the gpio ports are configurable with the gp0_ctrl and gp1_ctrl registers. the registers select whether a gpio will be used as an input or as an output, and if used as an output, the output configuration (cmos/open- drain). step description register comments 1 apply system full- scale n/a apply an input voltage that should result in a full-scale conversion result to the appropriate analog input(s). 2 select filter and rate filter (0x08) for best results, select a rate no faster than the rate that will be used for conversions. a slower rate will result in more accurate calibration. 3 select reference input ctrl (0x09) for best results, select a reference voltage equal to or near value that will be used for conversions. 4 set input multi - plexer mux_cntrl0 (0x0b) select inputs to which system full-scale is applied. 5 select gain and signal path pga (0x0e) for best results, select the signal path that will be used for conversions. select the gain that, when combined with the applied input voltage, yields a full-scale conversion result . 6 select clock source and format ctrl (0x11) for best results, select the clock source (internal or external) that will be used for conversions. if external clock is selected, ensure that the external clock is operating before beginning calibration. format selection doesnt affect results. 7 select system offset and start calibration cal_start write xxxxx101 to store in sys_gain_a register or xxxxx111 to store in sys_gain_b register. table 7d. example of system gain calibration maxim integrated 31 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
conversion data formats the conversion data format is selected by the format and u_bn bits in the ctrl register, as shown in table 7a . the unipolar/bipolar select (u_bn) bit selects whether the input range is bipolar or unipolar. a 1 in this bit loca - tion selects unipolar input range and a 0 selects bipolar input range. the format select (format) bit controls the data format when in bipolar mode (u_bn =0). unipolar data is always in straight binary format. the format bit has no effect in unipolar mode (u_bn = 1). in bipolar mode, if the format bit = 1, then the data format is off - set binary. if the format bit = 0, then the data format is twos complement. digital filter the configurable digital filter has selectable notch fre - quencies (50 and 60, 50, 60, or sinc4) and selectable data rates. the filter rejection and frequency response is determined by the linef and rate field settings in the filter register. the simultaneous 50hz/60hz rejection fir filter provides well over 90db rejection of 50hz and 60hz at 16sps and significant rejection of their harmonics. the 50hz and 60hz fir filter settings provide a lower level of attenua - tion for those frequencies, but at a faster conversion time than available with the simultaneous 50hz/ 60hz fir fil - ter. the sinc4 setting enables a 4th-order sinc filter that can operate at continuous data rates up to 1920sps, with the first notch at the continuous data rate. the available conversion rates are determined by the linef setting. note that data rate for a given rate setting is determined by the type of conversion selected in the conv_start or gp_conv register, based on a nominal clock period of 2.456mhz. in continuous conversion mode with linef = 11, the digital filter has a settling time of 4x the sample rate. the first sample will not be available until the expi - ration of that settling time. subsequent samples will be available at the listed sample rate. the filter sample rate is determined by the combination of linef and rate settings, as well as the type of conversion launched by the conv_start command. data rates and rejection specifications for all settings are summarized below. mode bipolar mode unipolar mode format 1 0 x u_bn 0 0 1 code description input voltage (v ainp -v ainn ) offset binary 2s complement input voltage (v ainp -v ainn ) straight binary (unipolar mode) positive full scale vref 0xffffff 0x7fffff v ref 0xffffff positive fs C 1lsb v ref (1-1/(2 23 -1)) 0xfffffe 0x7ffffe v ref (1-1/(2 24 -1)) 0xfffffe positive mid-scale v ref (1+1/(2 23 -1))/2 0xc00000 0x400000 v ref (1+1/(2 24 -1))/2 0x800000 positive 1 lsb v ref /(2 23 -1) 0x800001 0x000001 vref/(2 24 -1) 0x000001 0v 0x800000 0x000000 0v 0x000000 negative 1 lsb - v ref /(2 23 -1) 0x7fffff 0xffffff <0v 0x000000 negative fs + 1lsb -v ref 0x000001 0x800001 <0v 0x000000 negative fs - v ref (1+1/(2 23 -1)) 0x000000 0x800000 <0v 0x000000 table 8. conversion data formats maxim integrated 32 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
rate value filter type rejection (hz) data rate (sps) single cycle continuous duty cycle 0000 fir50/60 50/60hz 1.0 1.1 0.3 0001 fir50/60 50/60hz 2.0 2.1 0.5 0010 fir50/60 50/60hz 4.0 4.2 1.1 0011 fir50/60 50/60hz 8.0 8.4 2.1 0100-1111 fir50/60 50/60hz 16.0 16.8 4.2 rate value filter type rejection (hz) data rate (sps) single cycle continuous duty cycle 0000 fir50 50hz 1.3 1.3 0.3 0001 fir50 50hz 2.5 2.7 0.7 0010 fir50 50hz 5.0 5.3 1.3 0011 fir50 50hz 10.0 10.7 2.7 0100 fir50 50hz 20.0 21.3 5.3 0101-1111 fir50 50hz 35.6 40 10.0 rate value filter type rejection (hz) data rate (sps) single cycle continuous duty cycle 0000 fir60 60hz 1.3 1.3 0.3 0001 fir60 60hz 2.5 2.7 0.7 0010 fir60 60hz 5.0 5.3 1.3 0011 fir60 60hz 10.0 10.7 2.7 0100 fir60 60hz 20 21.3 5.3 0101-1111 fir60 60hz 35.6 40 10.0 rate value filter type rejection (hz) data rate (sps) single cycle continuous duty cycle 0000 sinc4 4 1 4 1 0001 sinc4 10 2.5 10 2.5 0010 sinc4 20 5 20 5 0011 sinc4 40 10 40 10 0100 sinc4 60 15 60 15 0101 sinc4 120 30 120 30 0110 sinc4 240 60 240 60 0111 sinc4 480 120 480 120 1000 sinc4 960 240 960 240 1001-1111 sinc4 1920 480 1920 480 table 9a. linef = 00 data rate and filter rejection settings table 9b. linef = 01 data rate and filter rejection settings table 9c. linef = 10 data rate and filter rejection settings table 9d. linef = 11 data rate and filter rejection settings maxim integrated 33 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sequencer the sequencer is a powerful feature that allows a sequence of commands to be programmed into the sequence buffer (c0-c52 registers). when a sequence is initiated by a write to the seq_start register or (when configured) a rising edge on a gpio pin, the sequencer will serially execute commands as if it were the spi master writing those commands to the control registers. the initiated sequence will begin executing at the address in the seq_addr or gp_seq_addr, depending on which is selected. sequences will execute until a pd command is encountered or until the sequencer is interrupted by a write from the spi master. if no pd command is encountered, the sequence will execute in a loop and wrap around from c52->c0. all c registers are '0000' by default, which corresponds to a 'pd:normal' commmand. pd commands function as a sequence stop. the completion of a sequence can be configured to generate an interrupt via the seq_rdy_ie bit. a wraparound, a pd execution, or a seq_start inside of a sequence will cause the assertion of seq_ rdy. as with a continuous conversion with conv_rdy, executing the sequencer in a loop will auto-clear seq_ rdy prior to re-asserting it. using a seq_start command within the sequencer microcode will function as a goto statement, enabling multiple continuous sequences to be programmed into the sequencers c register space. a conv_start, cal_start, or wait_start command will prevent the sequencer from advancing until the command is completed. sequence timing can be controlled with a wait_start command. wait durations should be programmed according to the settling time of the associated internal and external circuitry. the currently executing microcode address and data can be read back via the read-only caddr register. the caddr[6:0] can be read back at any time to determine the currently executing microcode address. a read of 0x00 indicates that the sequencer is inactive. values of 0x3a-0x6e indicate an active sequence. active sequences are exited by a write to any register, resetting the caddr register to 0x00. launching a sequence does not reset the control registers. all register states will be retained, either as a result of a prior write or a prior sequence execution. sequencer notes 1. registers with 24-bit data operands (uthresh, lthresh, self_off, status_ie, etc) are not supported in sequencer mode. programming a register that has a 24-bit operand into a c register will result in a '0000' or 'pd' being written to the c register. 2. writing a c address to a c register will result in a '0000' or 'pd' being written to the register. sequencer example below is shown a populated sequence buffer. three seq_start examples are discussed below: 1) the interface executes seq_start the sequencer will execute the commands shown (con - figure the input multiplexer, select buffered signal path, wait, convert and store in data location 1, configure the input multiplexer, wait, convert and store in data location 2, initiate a power down, issue a seq_rdy status, and halt the sequence at register c7. 2) the interface executes seq_start the sequencer will execute the commands starting at c8 and continuing through c48 in a loop until the the sequencer is interrupted with a write to the interface. this sequence configures the input multiplexer for various combinations of ain0 through ain0, performing a conver - sion with a variety of pga settings, storing the results in data0->data7. a seq_rdy will be asserted at the end of the sequence (c48) and deasserted when the sequence starts again (c8). 3) the interface executes seq_start the sequencer will execute the commands shown from address c49 (program the input multiplexer and filter, wait, perform a self-calibration) and wraparound continuing execution at c0. ultimately, the sequencer will initiate a power down, issue a seq_rdy status, and halt the sequence at register c7. maxim integrated 34 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sequencer register sequencer address command address bits 15:8 command name command data bits 7:0 comments c0 0x3a 0x0b mux_ctrl0 0x01 select ainp = ain0, ainn = ain1. c1 0x3b 0x0e pga 0x00 select buffered input, gain = 1. c2 0x3c 0x10 wait 0xd0 insert wait time of (wait_ext * 16) * (wait*16) * 407ns. assuming wait_ext = 0, wait time = 1.3ms. c3 0x3d 0x01 conv_ start 0x10 initiate a single conversion and send data to data1 register. c4 0x3e 0x0b mux_ctrl0 0x23 select ainp = ain2, ainn = ain3. c5 0x3f 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c6 0x40 0x01 conv_ start 0x20 initiate a single conversion and send data to data2 register. c7 0x41 0x00 pd 0x10 enter sleep mode, issue seq_rdy status, halt sequence. c8 0x42 0x0e pga 0x21 select pga, gain = 2. c9 0x43 0x0b mux_ctrl0 0x01 select ainp = ain0, ainn = ain1. c10 0x44 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c11 0x45 0x08 filter 0x04 select 50/60hz rejection, 16sps. c12 0x46 0x01 conv_ start 0x00 initiate a single conversion and send data to data0 register. c13 0x47 0x0e pga 0x22 select pga, gain = 4. c14 0x48 0x0b mux_ctrl0 0x23 select ainp = ain2, ainn = ain3. c15 0x49 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext=0). c16 0x4a 0x08 filter 0x04 select 50/60hz rejection, 16sps. c17 0x4b 0x01 conv_ start 0x10 initiate a single conversion and send data to data1 register. c18 0x4c 0x0e pga 0x20 select pga, gain = 1. c19 0x4d 0x0b mux_ctrl0 0x45 select ainp = ain4, ainn = ain5. c20 0x4e 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c21 0x4f 0x08 filter 0x04 select 50/60hz rejection, 16sps. c22 0x50 0x01 conv_ start 0x20 initiate a single conversion and send data to data2 register. c23 0x51 0x0e pga 0x02 select buffered input, digital gain = 4. c24 0x52 0x0b mux_ctrl0 0x03 select ainp = ain0, ainn = ain3. c25 0x53 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c26 0x54 0x08 filter 0x04 select 50/60hz rejection, 16sps. table 10. populated sequence register example. maxim integrated 35 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sequencer register sequencer address command address bits 15:8 command name command data bits 7:0 comments c27 0x55 0x01 conv_ start 0x30 initiate a single conversion and send data to data3 register. c28 0x56 0x0e pga 0x24 select pga, gain = 16. c29 0x57 0x0b mux_ctrl0 0x78 select ainp = ain7, ainn = ain8. c30 0x58 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c31 0x59 0x08 filter 0x04 select 50/60hz rejection, 16sps. c32 0x5a 0x01 conv_ start 0x40 initiate a single conversion and send data to data4 register. c33 0x5b 0x0e pga 0x22 select pga, gain = 4. c34 0x5c 0x0b mux_ctrl0 0x69 select ainp = ain6, ainn = ain9. c35 0x5d 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c36 0x5e 0x08 filter 0x04 select 50/60hz rejection, 16sps. c37 0x5f 0x01 conv_ start 0x50 initiate a single conversion and send data to data5 register. c38 0x60 0x0e pga 0x22 select pga, gain = 4. c39 0x61 0x0b mux_ctrl0 0x20 select ainp = ain2, ainn = ain0. c40 0x62 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c41 0x63 0x08 filter 0x04 select 50/60hz rejection, 16sps. c42 0x64 0x01 conv_ start 0x60 initiate a single conversion and send data to data6 register. c43 0x65 0x0e pga 0x27 select pga, gain = 128. c44 0x66 0x0b mux_ctrl0 0x19 select ainp = ain1, ainn = ain9. c45 0x67 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c46 0x68 0x08 filter 0x04 select 50/60hz rejection, 16sps. c47 0x69 0x01 conv_ start 0x70 initiate a single conversion and send data to data7 register. c48 0x6a 0x02 seq_start 0x42 loop back to sequencer address 0x42 and restart sequence. c49 0x6b 0x0b mux_ctrl0 0x26 select ainp = ain2, ainn = ain6. c50 0x6c 0x08 filter 0x04 select 50/60hz rejection, 16sps. c51 0x6d 0x10 wait 0xd0 insert wait time of 1.3ms (assuming wait_ext = 0). c52 0x6e 0x03 cal_start 0x00 perform a self-calibration. wrap around to c0 (0x3a) and continue. table 10. populated sequence register example. (continued) maxim integrated 36 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
spi interface the interface is mode 0 spi/qspi?/microwire?/dsp compatible. data is strobed in on sclk rising edges. the content of the spi operation consists of a one-byte register address and read/write command followed by a one, two, or three-byte control or data word. programming is by a variable cycle (dictated by the register byte width) spi instruction framed by a csb low interval. to abort a command sequence, the rise of csb must precede the updating rising edge of sclk. data out (dout) is updated on the falling edge of sclk. until power-on or other wakeup times have elapsed, reads and writes will have no effect. dout/intb this output serves a dual function. in addition to the serial-data output function, dout/intb also indicates the interrupt condition when csb is low. to find the interrupt state, assert csb low and sample the intb/dout output. when performing a device readback, the dout/intb pin will reflect the interrupt states until the 9th sclk falling edge, at which point it will transition to the dout data. spi transactions all transactions consist of a read/write bit, register address, and register data (returned or written). all registers are either 8, 16, or 24 bits in length. program word execution happens on either the 16th, 24th, or 32nd edge, depending on the programmed register word length. paired spi register reads and writes are not supported. writing to any register while a calibration or conversion is in progress will result in the calibration or conversion being aborted. readback of any register will not affect either calibration or conversion. registers are read and written msb first. there are three sets of registers for control, status, and data. the 8-bit registers control conversion and power modes, multiplexer connections, and other functions. the 24-bit registers contain conversion data, calibration coefficients, status information, and control over which status bits are reflected in interrupt outputs. the 16-bit registers contain the command addresses and data values for the sequencer. figure 2. spi timing diagram maxim integrated 37 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
register address byte write to this register (shown in clock cycles 0 through 7 in the spi timing diagram) to begin any read or write transaction. the r/wb bit selects whether the transaction is a read or write. the reg_addr bits select the address of the register to be written or read. there are three register maps, with register widths of 8, 16, and 24 bits. because register sizes are variable, the reg_addr bits also determine the length of the transaction. register address r/w size (bits) default value d7 d6 d5 d4 d3 d2 d1 d0 addr xx w 8 r/wb reg_addr[6:0] field name bit(s) default function 7:2 r/wb 7 r/wb description 0 write to the register at address reg_addr[6:0]. 1 read the register at address reg_addr[6:0]. reg_addr[6:0] 6:0 reg_addr[6:0 ] description read or write (based the value of r/wb) the register at this address. maxim integrated 38 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
register map 8-bit control registerspd (0x00) address name msb lsb control 0x00 pd[7:0] pd[1:0] 0x01 conv_start[7:0] dest[2:0] conv_type [1:0] 0x02 seq_start[7:0] 0x03 cal_start[7:0] cal_type[2:0] 0x04 gp0_ctrl[7:0] gp0_dir[1:0] gp0_isel[1:0] gp0_osel[2:0] 0x05 gp1_ctrl[7:0] gp1_dir[1:0] gp1_isel[1:0] gp1_osel[2:0] 0x06 gp_conv[7:0] gp_dest [2:0] gp_conv_type [1:0] 0x07 gp_seq_ addr[7:0] gp_seq_addr[6:0] 0x08 filter[7:0] re - served (0) linef[1:0] rate[3:0] 0x09 ctrl[7:0] extclk u_bn format ref - bufp_ en ref - bufn_ en ref_sel[2:0] 0x0a source[7:0] vbias_mode[1:0] brn_mode[1:0] idac_mode[3:0] 0x0b mux_ctrl0[7:0] ainp_sel[3:0] ainn_sel[3:0] 0x0c mux_ctrl1[7:0] idac1_sel[3:0] idac0_sel[3:0] 0x0d mux_ctrl2[7:0] vbias_ sel_7 vbias_ sel_6 vbias_ sel_5 vbias_ sel_4 vbias_ sel_3 vbias_ sel_2 vbias_ sel_1 vbias_ sel_0 0x0e pga[7:0] sig_path[1:0] gain[2:0] 0x0f wait_ext[7:0] wait_ext[7:0] 0x10 wait_start[7:0] maxim integrated 39 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
pd (0x00) this register selects the power-down state to be executed. while in a sequence, executing a power-down command will cause the sequencer to stop and issue a seq_rdy status. in standby or sleep mode, writing an asynchonous start command (wait_start, conv_start, seq_start, wait_start), will initiate wakeup, causing the pd state to change to normal mode. during wakeup, the pd register will read '10' and transition to '00' after the wakeup timer expires. asynchronous start operations will be delayed until the wakeup timer expires. conv_start (0x01) the conv_start register initiates conversions, selects the type of conversion to be performed (conv_type), and selects the register to which the conversion result will be written (dest). eight registers are available for adc conversion results. the three dest bits select which of these registers the current conversion will be stored in. the conv_type bits control what type of conversion is to be executed. if in pd: sleep or pd: standby mode, writing to this register changes the mode to pd: normal mode and then initiates the conversion. bit 7 6 5 4 3 2 1 0 field pd[1:0] reset 0x2 access type write, read bitfield bits description decode pd 1:0 00: normal mode 01: standby modepowers down all analog circuity, but not the internal voltage regulator 10: sleep modepowers down all analog circuitry including the internal voltage regulator (default) 11: resetall registers reset to por state (self clearing to 10) bit 7 6 5 4 3 2 1 0 field dest[2:0] conv_type[1:0] reset access type write, read write, read bitfield bits description decode dest 6:4 000: store result in data0 001: store result in data1 010: store result in data2 011: store result in data3 100: store result in data4 101: store result in data5 110: store result in data6 111: store result in data7 conv_type 1:0 00: single conversion 01: continuous conversions 10, 11: 1:4 duty cycled conversions (modulator low- power mode) maxim integrated 40 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
seq_start (0x02) a write to the seq_start register will immediately execute a sequence beginning at the sequencer address written to the seq_addr field. using a seq_start command within a sequence will function as a goto statement, enabling multiple continuous sequences to be programmed. writing an address that is outside of the sequencer's microcode address range (0x3a through 0x6e) will result in that write being ignored (no sequence will start). see the sequencer section for more information. if in pd:sleep or pd:standby mode, writing to this register changes the mode to pd:normal mode and then executes the sequence cal_start (0x03) writing to this register will execute a calibration as selected by the cal_type bits. successful completion of a calibration will result in an update of the corresponding calibration value registers. all calibrations are performed at the filter settings in the linef[1:0] and rate[3:0] register fields at the time the calibration is initiated. if in pd: sleep or pd: standby mode, writing to this register changes the mode to pd: normal mode and then initiates the calibration. bit 7 6 5 4 3 2 1 0 field cal_type[2:0] reset access type write, read bitfield bits description decode cal_type 2:0 000: performs a self-calibration. resulting offset calibration value is stored in the self_off register, and the 1x gain calibration value is stored in the self_gain_1 register. 001: performs a pga gain calibration at the currently programmed pga gain. a 'no op' will result if pga gain calibration is executed with the pga disabled via the sig_path register, or with the gain register set to 1x.the resulting gain calibration value is stored in the self_gain_[2-128] register corresponding to the currently programmed pga gain setting. 010: reserved 011: reserved 100: performs a system offset calibration. the resulting calibration value is stored in the sys_off_a register. 101: performs a system gain calibration. the resulting calibration value is stored in the sys_gain_a register. 110: performs a system offset calibration. the resulting calibration value is stored in the sys_off_b register. 111: performs a system gain calibration. the resulting calibration value is stored in the sys_gain_b register. maxim integrated 41 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
gp0_ctrl (0x04) the gp0_ctrl register controls the behavior of gpio0. writes of reserved values are ignored. the gpio_0 direction select field (gp0_dir) selects whether gpio_0 will behave as an input or an output. open-drain or cmos output max11410 may be selected. the gpi0_0 input select field (gp0_insel) selects the operation of the gpio_0 pin when configured as an input using the gp0_dir field. the gpio output select field, gp0_osel, controls the output operation of the gpio_0 pin when configured as an output using the gp0_dir field. when the gpio is set for rising-edge-triggered conversion start or rising-edge-triggered sequencer start, if in pd: sleep or pd: standby mode, the rising edge changes the mode to pd: normal mode and then initiates the conversion or sequence. the minimum pulse width for a gpio input is 2 x t clk . bit 7 6 5 4 3 2 1 0 field gp0_dir[1:0] gp0_isel[1:0] gp0_osel[2:0] reset access type write, read write, read write, read bitfield bits description decode gp0_dir 7:6 00: input mode, reference to v ddio (default) 01: reserved 10: output mode, open-drain output 11: output mode, cmos output gp0_isel 5:4 00: gpio_0 input disabled (default) 01: gpio_0 input confgured as rising-edge-triggered conversion start 10: gpio_0 input confgured as rising-edge-triggered conversion start 11: reserved gp0_osel 2:0 000: gpio_0 output disabled, high z (default) 001: gpio_0 output is confgured as intrb (active low) 010: gpio_0 output is confgured as intr (active high) 011: gpio_0 output is confgured as state logic 0 100: gpio_0 output is confgured as state logic 1 101: gpio_0 output is confgured as automatic low-side switch operation (cmos output mode overridden) 110: gpio_0 output is confgured as modulator active status 111: gpio_0 output is confgured as system clock (2.456mhz nominal) maxim integrated 42 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
gp1_ctrl (0x05) the gp1_ctrl register controls the behavior of gpio1. writes of reserved values are ignored. the gpio_1 direction select field (gp0_dir) selects whether gpio_1 will behave as an input or an output. open-drain or cmos output may be selected. the gpio_1 input select field, gp1_insel, selects the operation of the gpio_1 pin when configured as an input using the gp1_dir field. the gpio_1 output select field (gp1_osel) controls the output operation of the gpio_1 pin when configured as an output operation using the gp1_dir field. when the gpio is set for rising-edge-triggered conversion start or rising-edge-triggered sequencer start, if in pd: sleep or pd: standby mode, the rising edge changes the mode to pd: normal mode and then initiates the conversion or sequence. the minimum pulse width for a gpio input is 2 x t clk . bit 7 6 5 4 3 2 1 0 field gp1_dir[1:0] gp1_isel[1:0] gp1_osel[2:0] reset access type write, read write, read write, read bitfield bits description decode gp1_dir 7:6 00: input mode, reference to vddio (default) 01: reserved 10: output mode, open-drain output 11: output mode, cmos output gp1_isel 5:4 00: gpio_1 input disabled (default) 01: gpio_1 input confgured as rising-edge-triggered conversion start 10: gpio_1 input confgured as rising-edge-triggered conversion start 11: reserved gp1_osel 2:0 000: gpi1_0 output disabled, high z (default) 001: gpio_1 output is confgured as intrb (active low) 010: gpio_1 output is confgured as intr (active high) 011: gpio_1 output is confgured as state logic 0 100: gpio_1 output is confgured as state logic 1 101: gpio_1 output is confgured as system clock (2.456mhz nominal) 110: gpio_1 output is confgured as modulator active status 111: gpio_1 output is confgured as automatic low-side switch operation (cmos output mode overridden) maxim integrated 43 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
gp_conv (0x06) the gp_conv register selects the type of conversion to be performed when initiated by a gpio (when the gpio is configured as a conversion start input), and selects the register to which the conversion result will be written. writing to this register does not execute a conversion. when a gpio initiates a conversion, the conversion results will be written to the data register selected by the gpio conversion destination field (gp_dest). the gpio conversion type field selects the type of conversion that will be initiated by a gpio. gp_seq_addr (0x07) the gp_seq_addr register selects the target sequencer address when a sequence is initiated by a gpio (when the gpio is configured as a sequencer start input). writing to this register does not initiate a sequence. valid values are 0x3a - 0x6f. writes of invalid addresses will be ignored. bit 7 6 5 4 3 2 1 0 field gp_dest[2:0] gp_conv_type[1:0] reset access type write, read write, read bitfield bits description decode gp_dest 6:4 000: store result in data0 001: store result in data1 010: store result in data2 011: store result in data3 100: store result in data4 101: store result in data5 110: store result in data6 111: store result in data7 gp_conv_ type 1:0 00: single conversion 01: continuous conversions 10, 11: 1:4 duty cycled conversions (modulator low-power mode) bit 7 6 5 4 3 2 1 0 field gp_seq_addr[6:0] reset 0x3a access type write, read bitfield bits description gp_seq_addr 6:0 write the address of the sequencer (microcode) register at which a sequence should be initiated by a sequencer start gpio event. maxim integrated 44 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
filter (0x08) the filter register selects both the conversion data rate and the behavior of the digital filter. the linef field selects one of four digital filter options. the rate field select the data rate. the options available for the rate field are determined by the linef selection. see the tables in the digital gain section for details. ctrl (0x09) the ctrl register selects the clock source, the unipolar/bipolar data format, the reference inputs, and the reference buffers. the external clock enable (extclk) bit selects the whether the system clock source will be internal or external. setting extclk to '1' will override any settings in the gp0_ctrl register. a write to the extclk bit inside of a sequence will be ignored. changing clock sources inside of a sequence is not supported; a write to the extclk bit inside of a sequence will be ignored. the unipolar/bipolar select (u_bn) bit selects whether the input range is bipolar or unipolar. a 1 in this bit location selects unipolar input range and a 0 selects bipolar input range. the format select (format) bit controls the data format when in bipolar mode (u_bn = 0). unipolar data is always in straight binary format. the format bit has no effect in unipolar mode (u_bn = 1). in bipolar mode, if the format bit = 1, then the data format is offset binary. if the format bit = 0, then the data format is twos complement. (see table 6 .) writing to the format or u_bn bits does not change the values programmed in any threshold registers. however, it will affect the interpretation of these registers. when updating the format or u_bn bits, threshold registers should be re-written with values that agree with the new format. any input exceeding the available input range is limited to the minimum or maximum data value. the reference p-side and n-side buffer enable bits (refbufp and refbufn) control whether the reference input buffers will be enabled. bit 7 6 5 4 3 2 1 0 field reserved (0) linef[1:0] rate[3:0] reset access type write, read write, read write, read bitfield bits description decode reserved (0) 6 reserved; always set to 0. 0: always set to 0. linef 5:4 sets flter type. 00: simultaneous 50/60hz fir rejection (default) 01: 50hz fir rejection 10: 60hz fir rejection 11: sinc4 rate 3:0 sets conversion rate based on linef value. see table 9a through table 9d for details. maxim integrated 45 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
the reference select field (ref_sel) selects the reference source for the adc. available selections include the three differential reference input pairs, the analog power supply voltage, and the single-ended refp__ inputs. bit 7 6 5 4 3 2 1 0 field extclk u_bn format refbufp_ en refbufn_ en ref_sel[2:0] reset 0x0 0x0 0x0 0x0 0x0 0x1 access type write, read write, read write, read write, read write, read write, read bitfield bits description decode extclk 7 0: internal clock enabled (default) 1: external clock enabled via gpio_0 pin u_bn 6 0: bipolar input range (default) 1: unipolar input range format 5 0: twos complement format. applies only when bipolar input range is enabled. (default) 1: offset binary format refbufp_ en 4 0: power down the reference p-side buffer and bypass, driving the adc reference input directly from the reference mux (default) 1: enable the reference p-side buffer refbufn_ en 3 0: power down the reference n-side buffer and bypass, driving the adc reference input directly from the reference mux (default) 1: enable the reference n-side buffer ref_sel 2:0 000: ain0(ref0p)/ain1(ref0n) 001: ref1p/ref1n (default) 010: ref2p/ref2n 011: avdd/agnd 100: ain0(ref0p)/agnd (single-ended mode) 101: ref1p/agnd (single-ended mode) 110: ref2p/agnd (single-ended mode) 111: avdd/agnd maxim integrated 46 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
source (0x0a) the source register configures the excitation current sources, burnout current sources, and bias voltage source. the v bias mode control field (vbias_mode) selects the operating mode for the av dd /2 bias voltage source. the bias voltage may be supplied by an amplifier (active mode) or by a resistive divider (either 125k or 20k source resistance). the burnout current source select field (brn_mode) selects the nominal current value for the burnout detection current source and sink. three current values are available. the matched current source (idac_mode) field selects the nominal current output for the two matched excitation current sources. note that simultaneously enabling the idac and vbias sources on the same analog input is not supported. enabling v bias on an analog input with an idac enabled will clear the corresponding idac enable. enabling an idac on an analog input with v bias enabled will clear the corresponding v bias enable. bit 7 6 5 4 3 2 1 0 field vbias_mode[1:0] brn_mode[1:0] idac_mode[3:0] reset access type write, read write, read write, read bitfield bits description decode vbias_ mode 7:6 00: active mode (default) 01: high impedance; 125k output impedance 10: low impedance; 20k output impedance 11: low impedance; 20k output impedance brn_mode 5:4 00: powered down, burnout sources disabled (default) 01: 0.5a burnout current sources enabled 10: 1a burnout current sources enabled 11: 10a burnout current sources enabled idac_mode 3:0 0000: 10a (default) 0001: 50a 0010: 75a 0011: 100a 0100: 125a 0101: 150a 0110: 175a 0111: 200a 1000: 225a 1001: 250a 1010: 300a 1011: 400a 1100: 600a 1101: 800a 1110: 1200a 1111: 1600a maxim integrated 47 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
mux_ctrl0 (0x0b) the mux_ctrl0 register selects which analog inputs are connected to ainp and ainn. ainp_sel selects the multiplexer connection to the positive analog input, and ainn_sel selects the multiplexer connection to the negative analog input. ainp may also be connected to v dd and ainn may also be connected gnd. the default mode is for both ainp and ainn to be unconnected. bit 7 6 5 4 3 2 1 0 field ainp_sel[3:0] ainn_sel[3:0] reset 0xf 0xf access type write, read write, read bitfield bits description decode ainp_sel 7:4 0000: ainp = ain0 0001: ainp = ain1 0010: ainp = ain2 0011: ainp = ain3 0100: ainp = ain4 0101: ainp = ain5 0110: ainp = ain6 0111: ainp = ain7 1000: ainp = ain8 1001: ainp = ain9 1010: ainp = avdd 1011: ainn = unconnected 1100: ainn = unconnected 1101: ainn = unconnected 1110: ainn = unconnected 1111: ainn = unconnected (default) ainn_sel 3:0 0000: ainn = ain0 0001: ainn = ain1 0010: ainn = ain2 0011: ainn = ain3 0100: ainn = ain4 0101: ainn = ain5 0110: ainn = ain6 0111: ainn = ain7 1000: ainn = ain8 1001: ainn = ain9 1010: ainn = gnd 1011: ainn = unconnected 1100: ainn = unconnected 1101: ainn = unconnected 1110: ainn = unconnected 1111: ainn = unconnected (default) maxim integrated 48 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
mux_ctrl1 (0x0c) the mux_ctrl1 register enables the matched excitation current sources and selects which input each is connected to. idac1 and idac0 may be connected to any of the ten analog inputs, or may be powered down and unconnected. bit 7 6 5 4 3 2 1 0 field idac1_sel[3:0] idac0_sel[3:0] reset 0xf 0xf access type write, read write, read bitfield bits description decode idac1_sel 7:4 0000: ain0 0001: ain1 0010: ain2 0011: ain3 0100: ain4 0101: ain5 0110: ain6 0111: ain7 1000: ain8 1001: ain9 1010: unconnected; idac1 powered down. 1011: unconnected; idac1 powered down. 1100: unconnected; idac1 powered down. 1101: unconnected; idac1 powered down. 1110: unconnected; idac1 powered down. 1111: unconnected; idac1 powered down.(default) idac0_sel 3:0 0000: ain0 0001: ain1 0010: ain2 0011: ain3 0100: ain4 0101: ain5 0110: ain6 0111: ain7 1000: ain8 1001: ain9 1010: unconnected; idac0 powered down. 1011: unconnected; idac0 powered down. 1100: unconnected; idac0 powered down. 1101: unconnected; idac0 powered down. 1110: unconnected; idac0 powered down. 1111: unconnected; idac0 powered down.(default) maxim integrated 49 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
mux_ctrl2 (0x0d) this register enables of the connection of v bias source to the input mux. ain0 to ain7 are available for connection to the vbias source. each bit of the vbias_sel register corresponds to a switch enable for an analog input so the v bias source may be connected to more than one analog input. bit 7 6 5 4 3 2 1 0 field vbias_ sel_7 vbias_ sel_6 vbias_ sel_5 vbias_ sel_4 vbias_ sel_3 vbias_ sel_2 vbias_ sel_1 vbias_ sel_0 reset access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode vbias_ sel_7 7 0: unconnected 1: ain7 vbias_ sel_6 6 0: unconnected 1: ain6 vbias_ sel_5 5 0: unconnected 1: ain5 vbias_ sel_4 4 0: unconnected 1: ain4 vbias_ sel_3 3 0: unconnected 1: ain3 vbias_ sel_2 2 0: unconnected 1: ain2 vbias_ sel_1 1 0: unconnected 1: ain1 vbias_ sel_0 0 0: unconnected 1: ain0 maxim integrated 50 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
pga (0x0e) the pga register controls the signal path by enabling or disabling the input buffers and the pga, and by setting the gain. the signal path select field (sig_path) selects whether the multiplexer output will be connected to the modulator directly, through the low-power buffer, or through the pga. the gain field selects the analog gain setting for the pga. when when the input signal buffer or direct signal path is selected, this field selects the digital gain setting. when configured for digital gain (pga disabled) any gain setting higher than 4x will default to 4x. bit 7 6 5 4 3 2 1 0 field sig_path[1:0] gain[2:0] reset access type write, read write, read bitfield bits description decode sig_path 5:4 00: buffered, low-power, unity-gain path (pga disabled, digital gain) [default] 01: bypass path (signal buffer disabled,pga disabled, digital gain) 10: pga path (signal buffer disabled, analog gain) 11: reserved gain 2:0 000: 1 (default) 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 111: 128 maxim integrated 51 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
wait_ext (0x0f) this register extends the count range of the wait command. wait clocks = (wait_ext*16) * (wait * 16) for a 2.456mhz clock, the minimum wait period is 6.5sec. the maximum wait period using the wait extender is 6.77s. a write to the wait extension will not cause a wait command to execute. reading this register will return the written value. when wait_ext = 0x00, no wait extension is applied and the wait period is equal to (wait * 16). in the absence of a reset, the wait_ext selection applies to all subsequent wait_start commands. wait_start (0x10) a write to this register will execute a 'wait' operation with a clock count equal to wait clocks = (wait_ext x 16) * (wait x 16) for a 2.456mhz input clock, the minimum wait period is 6.5sec. the maximum wait period utilizing the wait extender is 6.77s. reading this register will return the current count value, as decremented since the last wait execution. writing to any register during a wait will abort the count operation, but will not reset the register. writing "0x00" to this register will result in a 'no op', and no wait_done status will be issued. if in pd: sleep or pd: standby mode, writing to this register changes the mode to pd: normal mode. bit 7 6 5 4 3 2 1 0 field wait_ext[7:0] reset 0x00 access type write, read bitfield bits description wait_ext 7:0 maxim integrated 52 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
24-bit control, data, and status registers address name msb lsb revision data 0x11 part_id[23:16] part_id[15:8] part_id[7:0] rev_id[2:0] system calibration registers 0x12 sysc_sel[23:16] C C C C C C C C sysc_sel[15:8] sysc_sel_7[1:0] sysc_sel_6[1:0] C C sysc_sel_4[1:0] sysc_sel[7:0] sysc_sel_3[1:0] sysc_sel_2[1:0] sysc_sel_1[1:0] sysc_sel_0[1:0] 0x13 sys_off_a[23:16] sys_off_a[23:16] sys_off_a[15:8] sys_off_a[15:8] sys_off_a[7:0] sys_off_a[7:0] 0x14 sys_off_b[23:16] sys_off_b[23:16] sys_off_b[15:8] sys_off_b[15:8] sys_off_b[7:0] sys_off_b[7:0] 0x15 sys_gain_a[23:16] sys_gain_a[23:16] sys_gain_a[15:8] sys_gain_a[15:8] sys_gain_a[7:0] sys_gain_a[7:0] 0x16 sys_gain_b[23:16] sys_gain_b[23:16] sys_gain_b[15:8] sys_gain_b[15:8] sys_gain_b[7:0] sys_gain_b[7:0] self-calibration registers 0x17 self_off[23:16] self_off[23:16] self_off[15:8] self_off[15:8] self_off[7:0] self_off[7:0] 0x18 self_gain_1[23:16] self_gain_1[23:16] self_gain_1[15:8] self_gain_1[15:8] self_gain_1[7:0] self_gain_1[7:0] 0x19 self_gain_2[23:16] self_gain_2[23:16] self_gain_2[15:8] self_gain_2[15:8] self_gain_2[7:0] self_gain_2[7:0] 0x1a self_gain_4[23:16] self_gain_4[23:16] self_gain_4[15:8] self_gain_4[15:8] self_gain_4[7:0] self_gain_4[7:0] maxim integrated 53 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
24-bit control, data, and status registers (continued) address name msb lsb 0x1b self_gain_8[23:16] self_gain_8[23:16] self_gain_8[15:8] self_gain_8[15:8] self_gain_8[7:0] self_gain_8[7:0] 0x1c self_gain_16[23:16] self_gain_16[23:16] self_gain_16[15:8] self_gain_16[15:8] self_gain_16[7:0] self_gain_16[7:0] 0x1d self_gain_32[23:16] self_gain_32[23:16] self_gain_32[15:8] self_gain_32[15:8] self_gain_32[7:0] self_gain_32[7:0] 0x1e self_gain_64[23:16] self_gain_64[23:16] self_gain_64[15:8] self_gain_64[15:8] self_gain_64[7:0] self_gain_64[7:0] 0x1f self_gain_128[23:16] self_gain_128[23:16] self_gain_128[15:8] self_gain_128[15:8] self_gain_128[7:0] self_gain_128[7:0] lower-threshold registers 0x20 lthresh0[23:16] lthresh0[23:16] lthresh0[15:8] lthresh0[15:8] lthresh0[7:0] lthresh0[7:0] 0x21 lthresh1[23:16] lthresh1[23:16] lthresh1[15:8] lthresh1[15:8] lthresh1[7:0] lthresh1[7:0] 0x22 lthresh2[23:16] lthresh2[23:16] lthresh2[15:8] lthresh2[15:8] lthresh2[7:0] lthresh2[7:0] 0x23 lthresh3[23:16] lthresh3[23:16] lthresh3[15:8] lthresh3[15:8] lthresh3[7:0] lthresh3[7:0] 0x24 lthresh4[23:16] lthresh4[23:16] lthresh4[15:8] lthresh4[15:8] lthresh4[7:0] lthresh4[7:0] 0x25 lthresh5[23:16] lthresh5[23:16] lthresh5[15:8] lthresh5[15:8] lthresh5[7:0] lthresh5[7:0] maxim integrated 54 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
24-bit control, data, and status registers (continued) address name msb lsb 0x26 lthresh6[23:16] lthresh6[23:16] lthresh6[15:8] lthresh6[15:8] lthresh6[7:0] lthresh6[7:0] 0x27 lthresh7[23:16] lthresh7[23:16] lthresh7[15:8] lthresh7[15:8] lthresh7[7:0] lthresh7[7:0] upper-threshold registers 0x28 uthresh0[23:16] uthresh0[23:16] uthresh0[15:8] uthresh0[15:8] uthresh0[7:0] uthresh0[7:0] 0x29 uthresh1[23:16] uthresh1[23:16] uthresh1[15:8] uthresh1[15:8] uthresh1[7:0] uthresh1[7:0] 0x2a uthresh2[23:16] uthresh2[23:16] uthresh2[15:8] uthresh2[15:8] uthresh2[7:0] uthresh2[7:0] 0x2b uthresh3[23:16] uthresh3[23:16] uthresh3[15:8] uthresh3[15:8] uthresh3[7:0] uthresh3[7:0] 0x2c uthresh4[23:16] uthresh4[23:16] uthresh4[15:8] uthresh4[15:8] uthresh4[7:0] uthresh4[7:0] 0x2d uthresh5[23:16] uthresh5[23:16] uthresh5[15:8] uthresh5[15:8] uthresh5[7:0] uthresh5[7:0] 0x2e uthresh6[23:16] uthresh6[23:16] uthresh6[15:8] uthresh6[15:8] uthresh6[7:0] uthresh6[7:0] 0x2f uthresh7[23:16] uthresh7[23:16] uthresh7[15:8] uthresh7[15:8] uthresh7[7:0] uthresh7[7:0] maxim integrated 55 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
24-bit control, data, and status registers (continued) conversion data registers 0x30 data0[23:16] data0[23:16] data0[15:8] data0[15:8] data0[7:0] data0[7:0] 0x31 data1[23:16] data1[23:16] data1[15:8] data1[15:8] data1[7:0] data1[7:0] 0x32 data2[23:16] data2[23:16] data2[15:8] data2[15:8] data2[7:0] data2[7:0] 0x33 data3[23:16] data3[23:16] data3[15:8] data3[15:8] data3[7:0] data3[7:0] 0x34 data4[23:16] data4[23:16] data4[15:8] data4[15:8] data4[7:0] data4[7:0] 0x35 data5[23:16] data5[23:16] data5[15:8] data5[15:8] data5[7:0] data5[7:0] 0x36 data6[23:16] data6[23:16] data6[15:8] data6[15:8] data6[7:0] data6[7:0] 0x37 data7[23:16] data7[23:16] data7[15:8] data7[15:8] data7[7:0] data7[7:0] status and interrupt registers 0x38 status[23:16] tor_7 tor_6 tor_5 tor_4 tor_3 tor_2 tor_1 tor_0 status[15:8] tur_7 tur_6 tur_5 tur_4 tur_3 tur_2 tur_1 tur_0 status[7:0] sys - gor wait_ done cal_ rdy seq_ rdy conv_ rdy 0x39 status_ie[23:16] tor_ ie_7 tor_ ie_6 tor_ ie_5 tor_ ie_4 tor_ ie_3 tor_ ie_2 tor_ ie_1 tor_ ie_0 status_ie[15:8] tur_ ie_7 tur_ ie_6 tur_ ie_5 tur_ ie_4 tur_ ie_3 tur_ ie_2 tur_ ie_1 tur_ ie_0 status_ie[7:0] sys - gor_ie data_ rdy_ie wait_ done_ ie cal_ rdy_ie seq_ rdy_ie conv_ rdy_ie maxim integrated 56 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
part_id (0x11) this register contains the silicon revision id. bit 23 22 21 20 19 18 17 16 field reset access type bit 15 14 13 12 11 10 9 8 field reset access type bit 7 6 5 4 3 2 1 0 field rev_id[2:0] reset access type read only bitfield bits description rev_id 2:0 silicon revision id. maxim integrated 57 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sysc_sel (0x12) there are two sets of system calibration registers, a (sys_off_a and sys_gain_a) and b (sys_off_b and sys_ gain_b). the sysc_sel bits select whether calibration set a, b, or neither set will be applied to the adc conversion result stored in the destination register, as selected by the this register. bit 23 22 21 20 19 18 17 16 field reset access type bit 15 14 13 12 11 10 9 8 field sysc_sel_7[1:0] sysc_sel_6[1:0] sysc_sel_4[1:0] reset access type write, read write, read write, read bit 7 6 5 4 3 2 1 0 field sysc_sel_3[1:0] sysc_sel_2[1:0] sysc_sel_1[1:0] sysc_sel_0[1:0] reset access type write, read write, read write, read write, read bitfield bits description decode sysc_ sel_7 15:14 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data7 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data7 register. 10, 11: system calibration disabled for data7 register. (only self-calibration will be applied.) sysc_ sel_6 13:12 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data6 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data6 register. 10, 11: system calibration disabled for data6 register. (only self-calibration will be applied.) sysc_ sel_4 9:8 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data4 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data4 register. 10, 11: system calibration disabled for data4 register. (only self-calibration will be applied.) maxim integrated 58 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
bitfield bits description decode sysc_ sel_3 7:6 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data3 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data3 register. 10, 11: system calibration disabled for data3 register. (only self-calibration will be applied.) sysc_ sel_2 5:4 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data2 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data2 register. 10, 11: system calibration disabled for data2 register. (only self-calibration will be applied.) sysc_ sel_1 3:2 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data1 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data1 register. 10, 11: system calibration disabled for data1 register. (only self-calibration will be applied.) sysc_ sel_0 1:0 00: sys_off_a & sys_gain_a calibration values are applied to the conversion result stored in data0 sysc_sel_7[1:0] register. (default) 01: sys_off_b & sys_gain_b calibration values are applied to the conversion result stored in data0 register. 10, 11: system calibration disabled for data0 register. (only self-calibration will be applied.) maxim integrated 59 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sys_off_a (0x13) the system offset a calibration value is subtracted from each conversion result, if selected by the sysc_dest_sel register. the data is always in 2s complement binary format, and is unaffected by the u_bn and format bits. writes to sys_ off_a are allowed. a value written to the register remains valid until either a new value is written or until an on-demand system-calibration operation is performed, which will overwrite the current value. the system offset calibration value applied to the selected destination register is subtracted from the conversion result after self-calibration, but before system gain correction. it is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. bit 23 22 21 20 19 18 17 16 field sys_off_a[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field sys_off_a[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field sys_off_a[7:0] reset access type write, read bitfield bits description sys_off_a 23:0 offset calibration value subtracted from selected conversion results. maxim integrated 60 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sys_off_b (0x14) the system offset b calibration value is subtracted from each conversion result, if selected by the sysc_dest_sel register. the data is always in 2s complement binary format, and is unaffected by the u_bn and format bits. writes to sys_ off_b are allowed. a value written to the register remains valid until either a new value is written or until an on-demand system-calibration operation is performed, which will over-write the current value. the system offset calibration value applied to the selected destination register is subtracted from the conversion result after self-calibration, but before system gain correction. it is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. bit 23 22 21 20 19 18 17 16 field sys_off_b[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field sys_off_b[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field sys_off_b[7:0] reset access type write, read bitfield bits description sys_off_b 23:0 offset calibration value subtracted from selected conversion results. maxim integrated 61 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sys_gain_a (0x15) the system gain calibration a value is used to scale the offset-corrected conversion result, if selected by the sysc_ dest_sel register. the format is fixed point, unsigned binary, and is unaffected by the u_bn and format bits. the binary point is located after the msb. the msb corresponds to 2 0 , and the lsb corresponds to 2 -23 . writes to this register are allowed. a value written to the register remains valid until either a new value is written or until an on-demand system-calibration operation is performed, which will overwrite the current value. the system gain calibration value scales the offset corrected result by up to 1.999999881x or can correct a gain error of C50%. the amount of positive gain error that can be corrected is determined by modulator overload characteristics, which may be as much as +25%. bit 23 22 21 20 19 18 17 16 field sys_gain_a[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field sys_gain_a[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field sys_gain_a[7:0] reset access type write, read bitfield bits description sys_gain_a 23:0 system gain a calibration value maxim integrated 62 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
sys_gain_b (0x16) the system gain calibration b value is used to scale the offset-corrected conversion result, if selected by the sysc_ dest_sel register. the format is fixed point, unsigned binary, and is unaffected by the u_bn and format bits. the binary point is located after the msb. the msb corresponds to 2 0 , and the lsb corresponds to 2 -23 . writes to this register are allowed. a value written to the register remains valid until either a new value is written or until an on-demand system-calibration operation is performed, which will overwrite the current value. the system gain calibration value scales the offset corrected result by up to 1.999999881x or can correct a gain error of -50%. the amount of positive gain error that can be corrected is determined by modulator overload characteristics, which may be as much as +25%. bit 23 22 21 20 19 18 17 16 field sys_gain_b[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field sys_gain_b[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field sys_gain_b[7:0] reset access type write, read bitfield bits description sys_gain_b 23:0 system gain b calibration values maxim integrated 63 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_off (0x17) the self-calibration offset value is subtracted from the conversion result, provided that the noselfoc bit is set to 0. the format is always 2s complement binary format, and is unaffected by the u_bn and format bits. writing to the self-calibration register is allowed. the value remains valid until either a new write is completed or an on-demand self- calibration operation is performed, which will overwrite the current value. the self-calibration offset value is subtracted from the conversion result before the self-calibration gain correction and before the system offset and gain correction. it is also applied prior to the 2x scale factor associated with unipolar mode. bit 23 22 21 20 19 18 17 16 field self_off[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_off[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_off[7:0] reset access type write, read bitfield bits description self_off 23:0 self-calibration offset value. maxim integrated 64 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_gain_1 (0x18) the self-calibration gain value scales the self-calibration offset-corrected conversion result before the system offset and gain calibration values have been applied. there is a self-gain calibration register for each of the eight selectable gain settings. the format is fixed point, unsigned binary, and is unaffected by the u_bn and format bits. the binary point is located after the msb. the msb corresponds to 2 0 , and the lsb corresponds to 2 -23 . a write to the system-calibration register is allowed. the written value remains valid until either a new write is completed or until an on-demand system- calibration operation is performed, which overwrites the current value. the self-calibration gain value scales the self- cal offset corrected conversion result by up to 2x or can correct a gain error of approximately C50%. the gain will be corrected to within 2 lsb. bit 23 22 21 20 19 18 17 16 field self_gain_1[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_1[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_1[7:0] reset access type write, read bitfield bits description self_gain_1 23:0 self-gain correction value for gain = 1. maxim integrated 65 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_gain_2 (0x19) self_gain_4 (0x1a) bit 23 22 21 20 19 18 17 16 field self_gain_2[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_2[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_2[7:0] reset access type write, read bitfield bits description self_gain_2 23:0 self-gain correction value for gain = 2. bit 23 22 21 20 19 18 17 16 field self_gain_4[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_4[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_4[7:0] reset access type write, read bitfield bits description self_gain_4 23:0 self-gain correction value for gain = 4. maxim integrated 66 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_gain_8 (0x1b) self_gain_16 (0x1c) bit 23 22 21 20 19 18 17 16 field self_gain_8[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_8[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_8[7:0] reset access type write, read bitfield bits description self_gain_8 23:0 self-gain correction value for gain = 8. bit 23 22 21 20 19 18 17 16 field self_gain_16[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_16[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_16[7:0] reset access type write, read bitfield bits description self_gain_16 23:0 self-gain correction value for gain = 16. maxim integrated 67 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_gain_32 (0x1d) self_gain_64 (0x1e) bit 23 22 21 20 19 18 17 16 field self_gain_32[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_32[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_32[7:0] reset access type write, read bitfield bits description self_gain_32 23:0 self-gain correction value for gain = 32. bit 23 22 21 20 19 18 17 16 field self_gain_64[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_64[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_64[7:0] reset access type write, read bitfield bits description self_gain_64 23:0 self-gain correction value for gain = 64. maxim integrated 68 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
self_gain_128 (0x1f) lthresh0 (0x20) lthresh0 holds the lower comparison threshold for the value in the data0 register. the comparison result is indicated by the tur_0 status bit. the comparison result indicated by tur_0 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field self_gain_128[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field self_gain_128[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field self_gain_128[7:0] reset access type write, read bitfield bits description self_gain_128 23:0 self-gain correction value for gain = 128. bit 23 22 21 20 19 18 17 16 field lthresh0[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh0[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh0[7:0] reset access type write, read bitfield bits description lthresh0 23:0 lower comparison threshold for data0 value. maxim integrated 69 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
lthresh1 (0x21) lthresh1 holds the lower comparison threshold for the value in the data1 register. the comparison result is indicated by the tur_1 status bit. the comparison result indicated by tur_1 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. lthresh2 (0x22) lthresh2 holds the lower comparison threshold for the value in the data2 register. the comparison result is indicated by the tur_2 status bit. the comparison result indicated by tur_2 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field lthresh1[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh1[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh1[7:0] reset access type write, read bitfield bits description lthresh1 23:0 lower comparison threshold for data1 value. bit 23 22 21 20 19 18 17 16 field lthresh2[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh2[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh2[7:0] reset access type write, read bitfield bits description lthresh2 23:0 lower comparison threshold for data2 value. maxim integrated 70 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
lthresh3 (0x23) lthresh3 holds the lower comparison threshold for the value in the data3 register. the comparison result is indicated by the tur_3 status bit. the comparison result indicated by tur_3 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. lthresh4 (0x24) lthresh4 holds the lower comparison threshold for the value in the data4 register. the comparison result is indicated by the tur_4 status bit. the comparison result indicated by tur_4 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field lthresh3[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh3[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh3[7:0] reset access type write, read bitfield bits description lthresh3 23:0 lower comparison threshold for data3 value. bit 23 22 21 20 19 18 17 16 field lthresh4[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh4[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh4[7:0] reset access type write, read bitfield bits description lthresh4 23:0 lower comparison threshold for data4 value. maxim integrated 71 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
lthresh5 (0x25) lthresh5 holds the lower comparison threshold for the value in the data5 register. the comparison result is indicated by the tur_5 status bit. the comparison result indicated by tur_5 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. lthresh6 (0x26) lthresh6 holds the lower comparison threshold for the value in the data6 register. the comparison result is indicated by the tur_6 status bit. the comparison result indicated by tur_6 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field lthresh5[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh5[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh5[7:0] reset access type write, read bitfield bits description lthresh5 23:0 lower comparison threshold for data5 value. bit 23 22 21 20 19 18 17 16 field lthresh6[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh6[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh6[7:0] reset access type write, read bitfield bits description lthresh6 23:0 lower comparison threshold for data6 value. maxim integrated 72 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
lthresh7 (0x27) lthresh7 holds the lower comparison threshold for the value in the data7 register. the comparison result is indicated by the tur_7 status bit. the comparison result indicated by tur_7 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. uthresh0 (0x28) uthresh0 holds the upper comparison threshold for the value in the data0 register. the comparison result is indicated by the tor_0 status bit. the comparison result indicated by tor_0 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field lthresh7[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field lthresh7[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field lthresh7[7:0] reset access type write, read bitfield bits description lthresh7 23:0 lower comparison threshold for data7 value. bit 23 22 21 20 19 18 17 16 field uthresh0[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh0[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh0[7:0] reset access type write, read bitfield bits description uthresh0 23:0 upper comparison threshold for data0 value. maxim integrated 73 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
uthresh1 (0x29) uthresh1 holds the upper comparison threshold for the value in the data1 register. the comparison result is indicated by the tor_1 status bit. the comparison result indicated by tor_1 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. uthresh2 (0x2a) uthresh2 holds the upper comparison threshold for the value in the data2 register. the comparison result is indicated by the tor_2 status bit. the comparison result indicated by tor_2 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field uthresh1[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh1[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh1[7:0] reset access type write, read bitfield bits description uthresh1 23:0 upper comparison threshold for data1 value. bit 23 22 21 20 19 18 17 16 field uthresh2[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh2[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh2[7:0] reset access type write, read bitfield bits description uthresh2 23:0 upper comparison threshold for data2 value. maxim integrated 74 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
uthresh3 (0x2b) uthresh3 holds the upper comparison threshold for the value in the data3 register. the comparison result is indicated by the tor_3 status bit. the comparison result indicated by tor_3 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. uthresh4 (0x2c) uthresh4 holds the upper comparison threshold for the value in the data4 register. the comparison result is indicated by the tor_4 status bit. the comparison result indicated by tor_4 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field uthresh3[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh3[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh3[7:0] reset access type write, read bitfield bits description uthresh3 23:0 upper comparison threshold for data3 value. bit 23 22 21 20 19 18 17 16 field uthresh4[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh4[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh4[7:0] reset access type write, read bitfield bits description uthresh4 23:0 upper comparison threshold for data4 value. maxim integrated 75 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
uthresh5 (0x2d) uthresh5 holds the upper comparison threshold for the value in the data5 register. the comparison result is indicated by the tor_5 status bit. the comparison result indicated by tor_5 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. uthresh6 (0x2e) uthresh6 holds the upper comparison threshold for the value in the data6 register. the comparison result is indicated by the tor_6 status bit. the comparison result indicated by tor_6 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. bit 23 22 21 20 19 18 17 16 field uthresh5[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh5[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh5[7:0] reset access type write, read bitfield bits description uthresh5 23:0 upper comparison threshold for data5 value. bit 23 22 21 20 19 18 17 16 field uthresh6[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh6[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh6[7:0] reset access type write, read bitfield bits description uthresh6 23:0 upper comparison threshold for data6 value. maxim integrated 76 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
uthresh7 (0x2f) uthresh7 holds the upper comparison threshold for the value in the data7 register. the comparison result is indicated by the tor_7 status bit. the comparison result indicated by tor_7 is affected by the u_bn and format bits. if the u_bn and/or format bits are changed, the threshold value should be changed accordingly. data0 (0x30) the adc conversion result is stored in data0 if this register is selected by the state of the dest or gp_dest register. bit 23 22 21 20 19 18 17 16 field uthresh7[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field uthresh7[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field uthresh7[7:0] reset access type write, read bitfield bits description uthresh7 23:0 upper comparison threshold for data7 value. bit 23 22 21 20 19 18 17 16 field data0[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data0[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data0[7:0] reset access type write, read bitfield bits description data0 23:0 conversion data. maxim integrated 77 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
data1 (0x31) the adc conversion result is stored in data1 if this register is selected by the state of the dest or gp_dest register. data2 (0x32) the adc conversion result is stored in data2 if this register is selected by the state of the dest or gp_dest register. bit 23 22 21 20 19 18 17 16 field data1[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data1[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data1[7:0] reset access type write, read bitfield bits description data1 23:0 conversion data. bit 23 22 21 20 19 18 17 16 field data2[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data2[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data2[7:0] reset access type write, read bitfield bits description data2 23:0 conversion data. maxim integrated 78 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
data3 (0x33) the adc conversion result is stored in data3 if this register is selected by the state of the dest or gp_dest register. data4 (0x34) the adc conversion result is stored in data4 if this register is selected by the state of the dest or gp_dest register. bit 23 22 21 20 19 18 17 16 field data3[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data3[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data3[7:0] reset access type write, read bitfield bits description data3 23:0 conversion data. bit 23 22 21 20 19 18 17 16 field data4[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data4[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data4[7:0] reset access type write, read bitfield bits description data4 23:0 conversion data. maxim integrated 79 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
data5 (0x35) the adc conversion result is stored in data5 if this register is selected by the state of the dest or gp_dest register. data6 (0x36) the adc conversion result is stored in data6 if this register is selected by the state of the dest or gp_dest register. bit 23 22 21 20 19 18 17 16 field data5[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data5[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data5[7:0] reset access type write, read bitfield bits description data5 23:0 conversion data. bit 23 22 21 20 19 18 17 16 field data6[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data6[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data6[7:0] reset access type write, read bitfield bits description data6 23:0 conversion data. maxim integrated 80 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
data7 (0x37) the adc conversion result is stored in data7 if this register is selected by the state of the dest or gp_dest register. status (0x38) the status register can be read to determine the state of the device and determine the cause of intb signal assertion. most status register bits are cleared by a status register read. the tor bits are threshold register over-range status bits. when one is set, it indicates that the corresponding data register value is greater than the value set by the uthresh register or the adc conversion result has created a digital under-range condition. tor will clear when the status register is read. tor register bits do not self-clear. the tur bits are threshold register under-range status bits. when one is set, it indicates that the corresponding data register value is less than the value set by the lthresh register or the adc conversion result has created a digital underrange condition. tur will clear when the status register is read. tur register bits do not self-clear. the system gain over-range status bit (sysgor) indicates that a system gain calibration was overrange. the sys_gain calibration coefficient has a maximum value of 1.9999999 (0xffffff). when set to 1, sysgor indicates that full-scale value out of the converter is likely not available. sys_gor will clear when the status register is read, or if a new system gain calibration yeilds a valid result. the data_rdy bit indicates that the data registers contain unread adc conversion results. this bit is cleared when all unread data registers have been read. unlike other status bits, data_rdy is not cleared by a status register read. the data_rdy status bit is a logical or of 8 internal register status bits that are set when new adc data is written to a data register, and are cleared when the corresponding data register is read. example 1: a conv_start is performed with 0x70 as the operand. the adc completes the single conversion. data7 contains new conversion data and data_rdy is set. next, the contents of the data7 register are read. this causes the corresponding internal register to clear, and the data_rdy status bit is cleared. example 2: a conv_start is performed with 0x61 as the operand. the adc is in a continuous-conversion mode, writing to the data6 register and setting the data_rdy status bit. the data_rdy bit remains set until the data6 register has been read. as the adc is continuously converting, the data_rdy bit will be set again as new data is written to the data6 register. bit 23 22 21 20 19 18 17 16 field data7[23:16] reset access type write, read bit 15 14 13 12 11 10 9 8 field data7[15:8] reset access type write, read bit 7 6 5 4 3 2 1 0 field data7[7:0] reset access type write, read bitfield bits description data7 23:0 conversion data. maxim integrated 81 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
example 3: the following sequence is written conv_start, 0x00 (data_rdy is set) conv_start, 0x20 conv_start, 0x40 conv_start, 0x60 data_rdy[0], data_rdy[2], data_rdy[4], and data_rdy[6] are set internally, thereby setting the data_rdy status bit after the first conversion is complete. the ata0, data2, data4, and data6 registers are then read. after the last data register is read, all corresponding internal registers are cleared, and the data_rdy status bit is cleared. the wait_done bit indicates that the wait operation has completed. this status is cleared by a read of the status register or a write to the wait_start register the cal_rdy bit indicates that a new calibration result is available in the sys_cal or self_cal registers. cal_rdy is cleared by a read of the status register or a write to the cal_start register. the seq_rdy bit indicates that an initiated sequence has completed at least one iteration. seq_rdy is cleared by a read of the status register, a write to the seq_start register (including within a sequence), or a sequence wraparound from c52->c0. the conv_rdy bit indicates that a new conversion result is available in the data registers. conv_rdy is cleared by a read of the status register, a write to the conv_start register (including within a sequence), or prior to the availability of a new conversion result in continuous or duty cycle mode. bit 23 22 21 20 19 18 17 16 field tor_7 tor_6 tor_5 tor_4 tor_3 tor_2 tor_1 tor_0 reset access type read only read only read only read only read only read only read only read only bit 15 14 13 12 11 10 9 8 field tur_7 tur_6 tur_5 tur_4 tur_3 tur_2 tur_1 tur_0 reset access type read only read only read only read only read only read only read only read only bit 7 6 5 4 3 2 1 0 field sysgor C C C wait_ done cal_rdy seq_rdy conv_rdy reset C C C access type write, read C C C write, read write, read write, read write, read bitfield bits description decode tor_7 23 0: normal operation 1: threshold overrange/digital overrange condition on channel 7. clears when the status register is read. tor_6 22 0: normal operation 1: threshold overrange/digital overrange condition on channel 6. clears when the status register is read. maxim integrated 82 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
bitfield bits description decode tor_5 21 0: normal operation 1: threshold overrange/digital overrange condition on channel 5. clears when the status register is read. tor_4 20 0: normal operation 1: threshold overrange/digital overrange condition on channel 4. clears when the status register is read. tor_3 19 0: normal operation 1: threshold overrange/digital overrange condition on channel 3. clears when the status register is read. tor_2 18 0: normal operation 1: threshold overrange/digital overrange condition on channel 2. clears when the status register is read. tor_1 17 0: normal operation 1: threshold overrange/digital overrange condition on channel 1. clears when the status register is read. tor_0 16 0: normal operation 1: threshold overrange/digital overrange condition on channel 0. clears when the status register is read. tur_7 15 0: normal operation 1: threshold underrange/digital underrange condition on channel 7. clears when the status register is read. tur_6 14 0: normal operation 1: threshold underrange/digital underrange condition on channel 6. clears when the status register is read. tur_5 13 0: normal operation 1: threshold underrange/digital underrange condition on channel 5. clears when the status register is read. tur_4 12 0: normal operation 1: threshold underrange/digital underrange condition on channel 4. clears when the status register is read. tur_3 11 0: normal operation 1: threshold underrange/digital underrange condition on channel 3. clears when the status register is read. tur_2 10 0: normal operation 1: threshold underrange/digital underrange condition on channel 2. clears when the status register is read. tur_1 9 0: normal operation 1: threshold underrange/digital underrange condition on channel 1. clears when the status register is read. maxim integrated 83 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
bitfield bits description decode tur_0 8 0: normal operation 1: threshold underrange/digital underrange condition on channel 0. clears when the status register is read. sysgor 7 0: no fault detected 1: a system gain calibration was overrange. clears when the status register is read. wait_done 3 0: no change 1: wait operation has completed. clears on a read of the status register or a write to the wait_start register cal_rdy 2 0: no change 1: calibration complete. new calibration result(s) available in the sys or self calibration registers. clears on a read of the status register or a write to the cal_start register. seq_rdy 1 0: no sequence completed, or status bit has been reset. 1: sequence has completed at least one iteration. cleared by a read of the status register, a write to the seq_start register (including within a sequence), or a sequence wraparound from c52->c0. conv_rdy 0 0: normal operation 1: new conversion result(s) available in the data registers. cleared by a read of the status register, a write to the conv_start register, or just prior to the availability of a new conversion result in continuous or duty cycle mode. maxim integrated 84 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
status_ie (0x39) the status_ie register enables or disables status events from appearing as a logic or of the int signal state. for every status register bit, there is a corresponding status_ie bit. this register allows the int signal to be used as a system interrupt for any or all system status sources. writing a 1 to a bit causes the corresponding status bit state to assert an interrupt. the specific cause of the interrupt can be discerned by reading the status register. an interrupt can be masked by disabling its corresponding enable bit in this register. the default value of this register is 0x000001, enabling only conv_rdy by default. bit 23 22 21 20 19 18 17 16 field tor_ie_7 tor_ie_6 tor_ie_5 tor_ie_4 tor_ie_3 tor_ie_2 tor_ie_1 tor_ie_0 reset access type write, read write, read write, read write, read write, read write, read write, read write, read bit 15 14 13 12 11 10 9 8 field tur_ie_7 tur_ie_6 tur_ie_5 tur_ie_4 tur_ie_3 tur_ie_2 tur_ie_1 tur_ie_0 reset access type write, read write, read write, read write, read write, read write, read read only write, read bit 7 6 5 4 3 2 1 0 field sysgor_ ie data_ rdy_ie wait_ done_ie cal_rdy_ ie seq_rdy_ ie conv_ rdy_ie reset access type write, read write, read write, read write, read write, read write, read bitfield bits description decode tor_ie_7 23 0: tor_7 does not affect int state. 1: int asserts when tor_7 = 1. tor_ie_6 22 0: tor_6 does not affect int state. 1: int asserts when tor_6 = 1. tor_ie_5 21 0: tor_5 does not affect int state. 1: int asserts when tor_5 = 1. tor_ie_4 20 0: tor_4 does not affect int state. 1: int asserts when tor_4 = 1. tor_ie_3 19 0: tor_3 does not affect int state. 1: int asserts when tor_0 = 1. tor_ie_2 18 0: tor_2 does not affect int state. 1: int asserts when tor_2 = 1. tor_ie_1 17 0: tor_1 does not affect int state. 1: int asserts when tor_1 = 1. tor_ie_0 16 0: tor_0 does not affect int state. 1: int asserts when tor_0 = 1. tur_ie_7 15 0: tur_7 does not affect int state. 1: int asserts when tur_7 = 1. maxim integrated 85 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
16-bit sequencer registers bitfield bits description decode tur_ie_6 14 0: tur_6 does not affect int state. 1: int asserts when tur_6 = 1. tur_ie_5 13 0: tur_5 does not affect int state. 1: int asserts when tur_5 = 1. tur_ie_4 12 0: tur_4 does not affect int state. 1: int asserts when tur_4 = 1. tur_ie_3 11 0: tur_3 does not affect int state. 1: int asserts when tur_3 = 1. tur_ie_2 10 0: tur_2 does not affect int state. 1: int asserts when tur_2 = 1. tur_ie_1 9 0: tur_1 does not affect int state. 1: int asserts when tur_1 = 1. tur_ie_0 8 0: tur_0 does not affect int state. 1: int asserts when tur_0 = 1. sysgor_ie 7 0: sysgor does not affect int state. 1: int asserts when sysgor = 1. data_ rdy_ie 4 0: data_rdy does not affect int state. 1: int asserts when data_rdy = 1. wait_ done_ie 3 0: wait_done does not affect int state. 1: int asserts when wait_done = 1. cal_rdy_ie 2 0: cal_rdy does not affect int state. 1: int asserts when cal_rdy = 1. seq_ rdy_ie 1 0: seq_rdy does not affect int state. 1: int asserts when seq_rdy = 1. conv_ rdy_ie 0 0: conv_rdy does not affect int state. 1: int asserts when conv_rdy = 1. address name msb lsb sequencer registers 0x3a c 0[15:8] reg_addr[6:0] c 0[7:0] reg_data[7:0] 0x3b c 1[15:8] reg_addr[6:0] c 1[7:0] reg_data[7:0] 0x3c c 2[15:8] reg_addr[6:0] c 2[7:0] reg_data[7:0] 0x3d c 3[15:8] reg_addr[6:0] c 3[7:0] reg_data[7:0] 0x3e c 4[15:8] reg_addr[6:0] c 4[7:0] reg_data[7:0] 0x3f c 5[15:8] reg_addr[6:0] c 5[7:0] reg_data[7:0] maxim integrated 86 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
address name msb lsb 0x40 c 6[15:8] reg_addr[6:0] c 6[7:0] reg_data[7:0] 0x41 c 7[15:8] reg_addr[6:0] c 7[7:0] reg_data[7:0] 0x42 c 8[15:8] reg_addr[6:0] c 8[7:0] reg_data[7:0] 0x43 c 9[15:8] reg_addr[6:0] c 9[7:0] reg_data[7:0] 0x44 c 10[15:8] reg_addr[6:0] c 10[7:0] reg_data[7:0] 0x45 c 11[15:8] reg_addr[6:0] c 11[7:0] reg_data[7:0] 0x46 c 12[15:8] reg_addr[6:0] c 12[7:0] reg_data[7:0] 0x47 c 13[15:8] reg_addr[6:0] c 13[7:0] reg_data[7:0] 0x48 c 14[15:8] reg_addr[6:0] c 14[7:0] reg_data[7:0] 0x49 c 15[15:8] reg_addr[6:0] c 15[7:0] reg_data[7:0] 0x4a c 16[15:8] reg_addr[6:0] c 16[7:0] reg_data[7:0] 0x4b c 17[15:8] reg_addr[6:0] c 17[7:0] reg_data[7:0] 0x4c c 18[15:8] reg_addr[6:0] c 18[7:0] reg_data[7:0] 0x4d c 19[15:8] reg_addr[6:0] c 19[7:0] reg_data[7:0] 0x4e c 20[15:8] reg_addr[6:0] c 20[7:0] reg_data[7:0] 0x4f c 21[15:8] reg_addr[6:0] c 21[7:0] reg_data[7:0] 0x50 c 22[15:8] reg_addr[6:0] c 22[7:0] reg_data[7:0] 0x51 c 23[15:8] reg_addr[6:0] c 23[7:0] reg_data[7:0] maxim integrated 87 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
address name msb lsb 0x52 c 24[15:8] reg_addr[6:0] c 24[7:0] reg_data[7:0] 0x53 c 25[15:8] reg_addr[6:0] c 25[7:0] reg_data[7:0] 0x54 c 26[15:8] reg_addr[6:0] c 26[7:0] reg_data[7:0] 0x55 c 27[15:8] reg_addr[6:0] c 27[7:0] reg_data[7:0] 0x56 c 28[15:8] reg_addr[6:0] c 28[7:0] reg_data[7:0] 0x57 c 29[15:8] reg_addr[6:0] c 29[7:0] reg_data[7:0] 0x58 c 30[15:8] reg_addr[6:0] c 30[7:0] reg_data[7:0] 0x59 c 31[15:8] reg_addr[6:0] c 31[7:0] reg_data[7:0] 0x5a c 32[15:8] reg_addr[6:0] c 32[7:0] reg_data[7:0] 0x5b c 33[15:8] reg_addr[6:0] c 33[7:0] reg_data[7:0] 0x5c c 34[15:8] reg_addr[6:0] c 34[7:0] reg_data[7:0] 0x5d c 35[15:8] reg_addr[6:0] c 35[7:0] reg_data[7:0] 0x5e c 36[15:8] reg_addr[6:0] c 36[7:0] reg_data[7:0] 0x5f c 37[15:8] reg_addr[6:0] c 37[7:0] reg_data[7:0] 0x60 c 38[15:8] reg_addr[6:0] c 38[7:0] reg_data[7:0] 0x61 c 39[15:8] reg_addr[6:0] c 39[7:0] reg_data[7:0] 0x62 c 40[15:8] reg_addr[6:0] c 40[7:0] reg_data[7:0] 0x63 c 41[15:8] reg_addr[6:0] c 41[7:0] reg_data[7:0] maxim integrated 88 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
address name msb lsb 0x64 c 42[15:8] reg_addr[6:0] c 42[7:0] reg_data[7:0] 0x65 c 43[15:8] reg_addr[6:0] c 43[7:0] reg_data[7:0] 0x66 c 44[15:8] reg_addr[6:0] c 44[7:0] reg_data[7:0] 0x67 c 45[15:8] reg_addr[6:0] c 45[7:0] reg_data[7:0] 0x68 c 46[15:8] reg_addr[6:0] c 46[7:0] reg_data[7:0] 0x69 c 47[15:8] reg_addr[6:0] c 47[7:0] reg_data[7:0] 0x6a c 48[15:8] reg_addr[6:0] c 48[7:0] reg_data[7:0] 0x6b c 49[15:8] reg_addr[6:0] c 49[7:0] reg_data[7:0] 0x6c c 50[15:8] reg_addr[6:0] c 50[7:0] reg_data[7:0] 0x6d c 51[15:8] reg_addr[6:0] c 51[7:0] reg_data[7:0] 0x6e c 52[15:8] reg_addr[6:0] c 52[7:0] reg_data[7:0] 0x6f caddr[15:8] caddr[7:0] caddr[6:0] maxim integrated 89 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
c (0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e) caddr (0x6f) bit 15 14 13 12 11 10 9 8 field reg_addr[6:0] reset access type write, read bit 7 6 5 4 3 2 1 0 field reg_data[7:0] reset access type write, read bitfield bits description reg_addr 14:8 write the address of an 8-bit control register to include it in the sequence. reg_data 7:0 write the command that corresponds to the register selected by the reg_addr feld. bit 15 14 13 12 11 10 9 8 field reset access type bit 7 6 5 4 3 2 1 0 field caddr[6:0] reset access type read only bitfield bits description caddr 6:0 address of currently executing sequence command. maxim integrated 90 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
typical application circuits ref1p ref1n ain0/ref0p input mul tiplexer reference mul tiplexer 10a- 1600a 0.5a, 1a, 10a 0.5a, 1a, 10a gnd 3 rd -order de lta- sigma modulat or digit al fil ters (fir & sinc) digit al control logic clock genera to r 1.8v regula to r ain1/ref0n ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ref2p ref2n gnd av dd agnd gpio0/ ext_clk gpio1 cs# sclk din dout/ int# vddre g capreg vddi o capp capn pga ref0p ref0n bias vol t age max1 1410 1nf 100nf 3.3v 1k 1k 100nf 3.3v rref 4k 1k 1k 1k 1k 1k 1k 1k 1k shor t for 2-wire rt d shor t for 2- and 3-wire rt d 3.3v 100nf a. tw o-r td te mperature measurement circuit maxim integrated 91 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
typical application circuits (continued) maxim integrated 92 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
two-rtd temperature measurement circuit (2- 3-, and 4-wire) in typical application circuit a , ain1 and ain2 serve as the analog inputs for measuring the voltage across the first rtd, with ain0 and ain3 providing the rtd excitation currents. ain5 and ain6 are the analog inputs for the second rtd, with ain4 and ain7 providing the rtd excitation current. up to 1000 (at 0c) rtds, such as pt1000s can be measured over a full 850c operating range. the 1k resistors provide over-voltage protection for the inputs. although not shown, a 100nf filter capacitor will normally be connected across ref1p and ref1n. a 100nf filter capacitor will be connected across ain1/ ain2, with a 10nf from ain1 to gnd and from ain2 to gnd. capacitors will be similarly connected to ain5 and ain6. if the first rtd is a 4-wire or 2-wire unit, set idac0 to source 200a from ain0. this current will flow through the rtd and through rref, creating a voltage drop of 800mv across rref. the voltage across rref serves as the reference voltage for measurement of the rtd resistance. because the same current flows through the rtd and rref, the conversion data will be the ratio of the rtd resistance to rref. note that any error in the value of rref will directly affect the accuracy of the rtd measurement, so use a low-drift, accurate resistor for rref. if a singletemperature system calibration is performed, rref may have a relaxed initial tolerance. note that, while the 4-wire connection can eliminate errors due to cable resistance, any lead resistance will add to the apparent rtd resistance measurement when using a 2-wire connection. therefore, the 2-wire connection is normally used only when the rtd is close to the circuit. if a 3-wire rtd is used, idac0 will again source current from ain0, and idac1 will source current from ain3. if the lead resistances are equal, the voltage drops across the two upper leads will be equal, and therefore the voltage measured between ain1 and ain2 will be equal to the rtd voltage. because both excitation currents will flow through rref, the current values should be reduced to 150a to maintain voltage headroom. the output code will be half the ratio of the rtd resistance to rref because 300a flows through rref, but only 150a flows through the rtd. thermocouple measurement circuit measuring temperature with a thermocouple requires two measurements. the thermocouple voltage is measured using a precision voltage reference. in addition, a separate sensor must measure the temperature at the cold junction C the point at which the thermocouple wires make contact with copper at the input connector. cold-junction temperature may be measured in a number of different wayswith a stand-alone temperature sensor, a thermistor, an rtd, or a diode-connected transistor. typical application circuit b uses an rtd to measure cold-junction temperature. 1k protection resistors connect the thermocouple output to ain4 and ain5. set the pga gain to an appropriate value for the thermocouple being used. for example, a k-type thermocouple produces a maximum output voltage of about 54mv. setting the pga gain to 32 results in a maximum pga output voltage of about 1.7v, which is appropriate for use with the 2.5v reference shown. bias the thermocouple to v dd /2 using the internal bias voltage generator. select ain5 as the pin to which the internal bias generator is connected. to detect an unconnected thermocouple or a broken thermocouple wire, enable the burnout current generator. an open circuit will result in an overrange input. to measure the cold-junction temperature using an rtd, set idac0 to source 200a from ain8. this current will flow through the rtd and through rref, creating a voltage drop of 800mv across rref. the voltage across rref serves as the reference voltage for measurement of the rtd resistance. because the same current flows through the rtd and rref, the conversion data will be the ratio of the rtd resistance to rref. note that any error in the value of rref will directly affect the accuracy of the rtd measurement, so use a low-drift, accurate resistor for rref. if a single-temperature system calibration is performed, rref may have a relaxed initial tolerance. because the rtd is close to the adc, a 2-wire rtd may be used. although not shown, a 100nf filter capacitor will normally be connected across ref1p and ref1n. a 100nf filter capacitor will be connected across ain4/ain5, with a 10nf from ain4 to gnd and from ain5 to gnd. capacitors will be similarly connected to ain8 and ain9. additional thermocouples may be connected to the unused inputs. maxim integrated 93 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
+denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. part number temp range pin- package top marking MAX11410ATI+ -40c to +125c 28 tqfn-ep* 11410a package type package code outline no. land pattern no. tqfn t2844+1 21-0139 90-00 35 ordering information chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated 94 max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga www.maximintegrated.com
revision number revision date description pages changed 0 5/16 initial release revision history ? 2016 maxim integrated products, inc. 95 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max11410 24-bit multi-channel low-power 1.9ksps delta-sigma adc with pga for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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